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→Default boot sequence
DM8148 provides several boot sequences selectable via BTMODE[4:0] bootstrap pins. In order to fully understand how boot work on Naon platform, please read [[Memory organization (Naon)|Memory organization]] first.
For a detailed explanation of DM814x/AM387x see their Technical Reference Manual (available from TI websize) at section ''ROM Code Memory and Peripheral Booting''.
By default, Naon provides the following configuration:
# SPI
# UART
# EMAC.
Bootrom tries each boot mode in sequence and stops when it find a valid boot code. Assuming that: * default configuration is not changed and ,* no boot MMC card is connected to processor's MMC1 interface, * and there's a valid boot code programmed in SPI memory the actual boot sequence performed by ARM core will be:
# bootrom: this is executed from internal ROM code memory
#* copied by U-Boot 1st stage from NOR flash memory connected to SPI0 port to SDRAM
#* executed from SDRAM.
If no boot code is available in SPI NOR flash (for the bootrom this means that the first sector read returns 0xFFFFFFFF) the bootrom tries UART and EMAC peripheral booting.
=== Boot sequence options ===
