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==Dataset==
[[File:FICS-PCB samples.png|border|500x500px|center|caption]]
[[File:Samples per class in Microscope and DSLR subsets.png|border|500x500px|center|caption]]
[[File:Dataset processing and augmentation.png|border|500x500px|center|caption]]
[[File:Image augmentation for training samples.png|border|500x500px|center|caption]]
==Models==
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{| align="center" style = "background: transparent; margin: auto; width: 60%;"
|-align="center"
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|[[File:Resnet50 cores utilization.png|border|500x500px|none]]
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|[[File:Resnet50 DPU latency.png|border|500x500px|none]]
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|-align="center" valign="top"
|width="25"|
|width="100"|Utilization of CPU and DPU cores of ResNet50 model for 1, 2, and 4 threads
|width="25"|
|width="100"|DPU latency of ResNet50 model for 1, 2, and 4 threads
|width="25"|
|}
===ResNet101===
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|}
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<!--Start of table definition-->
{|style="background:transparent; color:black" border="0" height="550" align="center" valign="bottom" cellpadding=10px cellspacing=0px
|-align="center"
|
|[[File:Resnet101 cores utilization.png|border|500x500px|none]]
|
|[[File:Resnet101 DPU latency.png|border|500x500px|none]]
|
|-align="center" valign="top"
|width="25"|
|width="100"|Utilization of CPU and DPU cores of ResNet101 model for 1, 2, and 4 threads
|width="25"|
|width="100"|DPU latency of ResNet101 model for 1, 2, and 4 threads
|width="25"|
|}
|}
|}
<!--Start of table definition-->
{|style="background:transparent; color:black" border="0" height="550" align="center" valign="bottom" cellpadding=10px cellspacing=0px
|-align="center"
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|[[File:Resnet152 cores utilization.png|border|500x500px|none]]
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|[[File:Resnet152 DPU latency.png|border|500x500px|none]]
|
|-align="center" valign="top"
|width="25"|
|width="100"|Utilization of CPU and DPU cores of ResNet152 model for 1, 2, and 4 threads
|width="25"|
|width="100"|DPU latency of ResNet152 model for 1, 2, and 4 threads
|width="25"|
|}
===InceptionV4===
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{| align="center" style = "background: transparent; margin: auto; width: 60%;"
|}
|}
<!--Start of table definition-->
{|style="background:transparent; color:black" border="0" height="550" align="center" valign="bottom" cellpadding=10px cellspacing=0px
|-align="center"
|
|[[File:Inception v4 cores utilization.png|border|500x500px|none]]
|
|[[File:Inception v4 DPU latency.png|border|500x500px|none]]
|
|-align="center" valign="top"
|width="25"|
|width="100"|Utilization of CPU and DPU cores of InceptionV4 model for 1, 2, and 4 threads
|width="25"|
|width="100"|DPU latency of InceptionV4 model for 1, 2, and 4 threads
|width="25"|
|}
===Inception ResNet V1===
|}
|}
<!--Start of table definition-->
{|style="background:transparent; color:black" border="0" height="550" align="center" valign="bottom" cellpadding=10px cellspacing=0px
|-align="center"
|
|[[File:Inception resnet v1 cores utilization.png|border|500x500px|none]]
|
|[[File:Inception resnet v1 DPU latency.png|border|500x500px|none]]
|
|-align="center" valign="top"
|width="25"|
|width="100"|Utilization of CPU and DPU cores of Inception ResNet V1 model for 1, 2, and 4 threads
|width="25"|
|width="100"|DPU latency of Inception ResNet V1 model for 1, 2, and 4 threads
|width="25"|
|}
===Inception ResNet V2===
|}
|}
<!--Start of table definition-->
{|style="background:transparent; color:black" border="0" height="550" align="center" valign="bottom" cellpadding=10px cellspacing=0px
|-align="center"
|
|[[File:Inception resnet v2 cores utilization.png|border|500x500px|none]]
|
|[[File:Inception resnet v2 DPU latency.png|border|500x500px|none]]
|
|-align="center" valign="top"
|width="25"|
|width="100"|Utilization of CPU and DPU cores of Inception ResNet V2 model for 1, 2, and 4 threads
|width="25"|
|width="100"|DPU latency of Inception ResNet V2 model for 1, 2, and 4 threads
|width="25"|
|}
==Comparison==
