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Created page with "<section begin=History/> {| style="border-collapse:collapse; " ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |- ! style="borde..."
<section begin=History/>
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Sep 2020
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
|-
|}
<section end=History/>
<section begin=Body/>
== Processor and memory subsystem ==
The heart of ORCA module is composed by the following components:
*i.MX8M Plus SoC application processor
* Power supply unit
* LPDDR4 memory bank
* eMMC or NAND flash banks
* Connectors:
** 1 x 260 pins SO-DIMM edge connector with interfaces signals
This chapter shortly describes the main ORCA components.
=== Processor Info ===
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" |'''Processor'''
| align="center" style="background:#f0f0f0;" |'''i.MX8M Plus'''
|-
|# Cores
|4x Arm® Cortex®-A53
1x Arm® Cortex®-M7
|-
|Clock
|1.8 GHz
|-
|L2
Cache
|512 KB
|-
|LPDDR4
| 32 bit @ 2000 MHz
(LPDDR4-4000)
|-
|GPU
| 3D: Vivante GC 7000UL (2 Shader)<br>2D: Vivante GC520L<br>
OpenGL ES 3.1<br>Vulkan<br>Open VG 1.1<br>Open CL 1.2
|-
|VPU
| 1080p60 H.265, H.264, VP9, VP8 decoder<br>1080p60 H.265, H.264 encoder
|-
|NPU
| 2.25 TOP/s Neural Processing Unit
|-
|Display Controller
| Dual Channel LVDS up to 1080p60
|-
|Video Output
| 1x HDMI 2.0a<br>1x MIPI-DSI (4-lanes)
|-
|Camera Input
| colspan="2" |2x MIPI CSI (4-lanes each)<br>2x ISP
|-
|Ethernet
| 2x 10/100/1000 Mbit/s controller with AVB and IEEE1588
|-
|PCIe
| 1x PCIe 3 (1-lane)
|-
|USB
| 2x USB 2.0/3.0
|-
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M Plus
|}
=== RAM memory bank ===
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
|-
| '''Size max'''||8 GB
|-
| '''Width'''||32 bit
|-
| '''Speed'''||2000 MHz
|-
|}
=== eMMC flash bank ===
On board main storage memory eMMC is connected to the SDIO3 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||SDIO3
|-
| '''Size min'''||4 GB
|-
| '''Size max'''||64 GB
|-
| '''Bootable'''||Yes
|-
|}
=== NAND flash bank ===
{| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;"
| [[File:TBD.png|30px]]
| '''Section not completed yet'''
|}
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Raw NAND flash controller
|-
| '''Page size'''|| TBD
|-
| '''Size min'''||TBD
|-
| '''Size max'''||TBD
|-
| '''Width'''||8 bit
|-
| '''Chip select'''||TBD
|-
| '''Bootable'''||Yes
|-
|}
=== Memory map ===
For detailed information, please refer to chapter 2 “Memory Maps” of the [https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8m-plus-arm-cortex-a53-machine-learning-vision-multimedia-and-industrial-iot:IMX8MPLUS?tab=Documentation_Tab i.MX8M Plus Applications Processor Reference Manual]
=== Power supply unit ===
ORCA embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
----
[[Category:ORCA]]
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Sep 2020
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
|-
|}
<section end=History/>
<section begin=Body/>
== Processor and memory subsystem ==
The heart of ORCA module is composed by the following components:
*i.MX8M Plus SoC application processor
* Power supply unit
* LPDDR4 memory bank
* eMMC or NAND flash banks
* Connectors:
** 1 x 260 pins SO-DIMM edge connector with interfaces signals
This chapter shortly describes the main ORCA components.
=== Processor Info ===
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" |'''Processor'''
| align="center" style="background:#f0f0f0;" |'''i.MX8M Plus'''
|-
|# Cores
|4x Arm® Cortex®-A53
1x Arm® Cortex®-M7
|-
|Clock
|1.8 GHz
|-
|L2
Cache
|512 KB
|-
|LPDDR4
| 32 bit @ 2000 MHz
(LPDDR4-4000)
|-
|GPU
| 3D: Vivante GC 7000UL (2 Shader)<br>2D: Vivante GC520L<br>
OpenGL ES 3.1<br>Vulkan<br>Open VG 1.1<br>Open CL 1.2
|-
|VPU
| 1080p60 H.265, H.264, VP9, VP8 decoder<br>1080p60 H.265, H.264 encoder
|-
|NPU
| 2.25 TOP/s Neural Processing Unit
|-
|Display Controller
| Dual Channel LVDS up to 1080p60
|-
|Video Output
| 1x HDMI 2.0a<br>1x MIPI-DSI (4-lanes)
|-
|Camera Input
| colspan="2" |2x MIPI CSI (4-lanes each)<br>2x ISP
|-
|Ethernet
| 2x 10/100/1000 Mbit/s controller with AVB and IEEE1588
|-
|PCIe
| 1x PCIe 3 (1-lane)
|-
|USB
| 2x USB 2.0/3.0
|-
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M Plus
|}
=== RAM memory bank ===
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
|-
| '''Size max'''||8 GB
|-
| '''Width'''||32 bit
|-
| '''Speed'''||2000 MHz
|-
|}
=== eMMC flash bank ===
On board main storage memory eMMC is connected to the SDIO3 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||SDIO3
|-
| '''Size min'''||4 GB
|-
| '''Size max'''||64 GB
|-
| '''Bootable'''||Yes
|-
|}
=== NAND flash bank ===
{| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;"
| [[File:TBD.png|30px]]
| '''Section not completed yet'''
|}
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Raw NAND flash controller
|-
| '''Page size'''|| TBD
|-
| '''Size min'''||TBD
|-
| '''Size max'''||TBD
|-
| '''Width'''||8 bit
|-
| '''Chip select'''||TBD
|-
| '''Bootable'''||Yes
|-
|}
=== Memory map ===
For detailed information, please refer to chapter 2 “Memory Maps” of the [https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8m-plus-arm-cortex-a53-machine-learning-vision-multimedia-and-industrial-iot:IMX8MPLUS?tab=Documentation_Tab i.MX8M Plus Applications Processor Reference Manual]
=== Power supply unit ===
ORCA embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
----
[[Category:ORCA]]