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==SODIMM J1 ODD pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize" | Pin
! latexfontsize="scriptsize" | Pin Name
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |Voltage domain
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
|-
|J1.1
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.3
|3.3VIN
|INPUT VOLTAGE
| -
|3.3VIN
|S
|
|
|
|-
|J1.5
|3.3VIN
|INPUT VOLTAGE
| -
|3.3VIN
|S
|
|
|
|-
|J1.7
|3.3VIN
|INPUT VOLTAGE
| -
|3.3VIN
|S
|
|
|
|-
|J1.9
|3.3VIN
|INPUT VOLTAGE
| -
|3.3VIN
|S
|
|
|
|-
|J1.11
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.13
|ETH0_LED1
|LAN.LED1/PME_N1
|17
|NVCC_1V8
|I/O
|Must be level translated if used @ 3V3
Internally pulled-up to 1.8V during bootstrap
|
|
|-
|J1.15
|ETH0_LED2
|LAN.LED2
|15
|NVCC_1V8
|I/O
|Must be level translated if used @ 3V3
Internally pulled-up to 1.8V during bootstrap
|
|
|-
|J1.17
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.19
|ETH0_TXRX0_P
|LAN.TXRXP_A
|2
| -
|D
|
|
|
|-
|J1.21
|ETH0_TXRX0_M
|LAN.TXRXM_A
|3
| -
|D
|
|
|
|-
|J1.23
|ETH0_TXRX1_P
|LAN.TXRXP_B
|5
| -
|D
|
|
|
|-
|J1.25
|ETH0_TXRX1_M
|LAN.TXRXM_B
|6
| -
|D
|
|
|
|-
|J1.27
|ETH0_TXRX2_P
|LAN.TXRXP_C
|7
| -
|D
|
|
|
|-
|J1.29
|ETH0_TXRX2_M
|LAN.TXRXM_C
|8
| -
|D
|
|
|
|-
|J1.31
|ETH0_TXRX3_P
|LAN.TXRXP_D
|10
| -
|D
|
|
|
|-
|J1.33
|ETH0_TXRX3_M
|LAN.TXRXM_D
|11
| -
|D
|
|
|
|-
|J1.35
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="4" |J1.37
| rowspan="4" |GPIO1_IO00
| rowspan="4" |CPU.GPIO1_IO00
| rowspan="4" |AG14
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|GPIO1_IO00
|-
|ALT1
|CCM_ENET_PHY_REF_CLK_ROOT
|-
|ALT5
|CCM_REF_CLK_32K
|-
|ALT6
|CCM_EXT_CLK1
|-
| rowspan="4" |J1.39
| rowspan="4" |GPIO1_IO01
| rowspan="4" |CPU.GPIO1_IO01
| rowspan="4" |AF14
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for ETH PHY reset, do not connect
|ALT0
|GPIO1_IO01
|-
|ALT1
|PWM1_OUT
|-
|ALT5
|CCM_REF_CLK_24M
|-
|ALT6
|CCM_EXT_CLK2
|-
| rowspan="3" |J1.41
| rowspan="3" |SPDIF_EXT_CLK
| rowspan="3" |CPU.SPDIF_EXT_CLK
| rowspan="3" |AF8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SPDIF1_EXT_CLK
|-
|ALT1
|PWM1_OUT
|-
|ALT5
|GPIO5_IO05
|-
| rowspan="3" |J1.43
| rowspan="3" |GPIO1_IO13
| rowspan="3" |CPU.GPIO1_IO13
| rowspan="3" |AD9
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|GPIO1_IO13
|-
|ALT1
|USB1_OTG_OC
|-
|ALT5
|PWM2_OUT
|-
| rowspan="2" |J1.45
| rowspan="2" |GPIO1_IO11
| rowspan="2" |CPU.GPIO1_IO11
| rowspan="2" |AC10
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |Internally used for ETH CLK enable, do not connect
|ALT0
|GPIO1_IO11
|-
|ALT1
|USB1_OTG_ID
|-
| rowspan="3" |J1.47
| rowspan="3" |ECSPI2_SCLK
| rowspan="3" |CPU.ECSPI2_SCLK
| rowspan="3" |E6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|ECSPI2_SCLK
|-
|ALT1
|UART4_RX
|-
|ALT5
|GPIO5_IO10
|-
| rowspan="3" |J1.49
| rowspan="3" |ECSPI2_MOSI
| rowspan="3" |CPU.ECSPI2_MOSI
| rowspan="3" |B8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|ECSPI2_MOSI
|-
|ALT1
|UART4_TX
|-
|ALT5
|GPIO5_IO11
|-
| rowspan="3" |J1.51
| rowspan="3" |GPIO1_IO08
| rowspan="3" |CPU.GPIO1_IO08
| rowspan="3" |AG10
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|GPIO1_IO08
|-
|ALT1
|ENET1_1588_EVENT0_IN
|-
|ALT5
|USDHC2_RESET_B
|-
| rowspan="4" |J1.53
| rowspan="4" |GPIO1_IO09
| rowspan="4" |CPU.GPIO1_IO09
| rowspan="4" |AF10
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|GPIO1_IO09
|-
|ALT1
|ENET1_1588_EVENT0_OUT
|-
|ALT4
|USDHC3_RESET_B
|-
|ALT5
|SDMA2_EXT_EVENT0
|-
| rowspan="3" |J1.55
| rowspan="3" |ECSPI2_MISO
| rowspan="3" |CPU.ECSPI2_MISO
| rowspan="3" |A8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|ECSPI2_MISO
|-
|ALT1
|UART4_CTS_B
|-
|ALT5
|GPIO5_IO12
|-
|J1.57
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="3" |J1.59
| rowspan="3" |ECSPI2_SS0
| rowspan="3" |CPU.ECSPI2_SS0
| rowspan="3" |A6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|ECSPI2_SS0
|-
|ALT1
|UART4_RTS_B
(Configure register IOMUXC_UART4_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO5_IO13
|-
| rowspan="3" |J1.61
| rowspan="3" |GPIO1_IO05
| rowspan="3" |CPU.GPIO1_IO05
| rowspan="3" |AF12
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connect
Pulled-up to NVCC_3V3
|ALT0
|GPIO1_IO05
|-
|ALT1
|M4_NMI
|-
|ALT5
|CCM_PMIC_READY
|-
| rowspan="4" |J1.63
| rowspan="4" |SAI5_RXD0
| rowspan="4" |CPU.SAI5_RXD0
| rowspan="4" |AD18
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI5_RX_DATA0
( Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT0)
|-
|ALT1
|SAI1_TX_DATA2
|-
|ALT4
|PDM_BIT_STREAM0
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT4)
|-
|ALT5
|GPIO3_IO21
|-
| rowspan="6" |J1.65
| rowspan="6" |SAI5_RXD1
| rowspan="6" |CPU.SAI5_RXD1
| rowspan="6" |AC14
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |
|ALT0
|SAI5_RX_DATA1
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT0)
|-
|ALT1
|SAI1_TX_DATA3
|-
|ALT2
|SAI1_TX_SYNC
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
|-
|ALT3
|SAI5_TX_SYNC
(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT3)
|-
|ALT4
|PDM_BIT_STREAM1
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT4)
|-
|ALT5
|GPIO3_IO22
|-
| rowspan="4" |J1.67
| rowspan="4" |GPIO1_IO06
| rowspan="4" |CPU.GPIO1_IO06
| rowspan="4" |AG11
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
|ALT0
|GPIO1_IO06
|-
|ALT1
|ENET1_MDC
|-
|ALT5
|USDHC1_CD_B
|-
|ALT6
|CCM_EXT_CLK3
|-
| rowspan="4" |J1.69
| rowspan="4" |SAI2_RXC
| rowspan="4" |CPU.SAI2_RXC
| rowspan="4" |AB22
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI2_RX_BCLK
|-
|ALT1
|SAI5_TX_BCLK
(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT4
|UART1_RX
|-
|ALT5
|GPIO4_IO22
|-
| rowspan="6" |J1.71
| rowspan="6" |SAI2_RXFS
| rowspan="6" |CPU.SAI2_RXFS
| rowspan="6" |AC19
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |
|ALT0
|SAI2_RX_SYNC
|-
|ALT1
|SAI5_TX_SYNC
(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|ALT2
|SAI5_TX_DATA1
|-
|ALT3
|SAI2_RX_DATA1
|-
|ALT4
|UART1_TX
|-
|ALT5
|GPIO4_IO21
|-
|J1.73
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="2" |J1.75
| rowspan="2" |SD2_DATA0
| rowspan="2" |CPU.SD2_DATA0
| rowspan="2" |AB23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_DATA0
|-
|ALT5
|GPIO2_IO15
|-
| rowspan="2" |J1.77
| rowspan="2" |SD2_DATA1
| rowspan="2" |CPU.SD2_DATA1
| rowspan="2" |AB24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_DATA1
|-
|ALT5
|GPIO2_IO16
|-
| rowspan="2" |J1.79
| rowspan="2" |SD2_DATA2
| rowspan="2" |CPU.SD2_DATA2
| rowspan="2" |V24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_DATA2
|-
|ALT5
|GPIO2_IO17
|-
| rowspan="2" |J1.81
| rowspan="2" |SD2_DATA3
| rowspan="2" |CPU.SD2_DATA03
| rowspan="2" |V23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_DATA3
|-
|ALT5
|GPIO2_IO18
|-
| rowspan="2" |J1.83
| rowspan="2" |SD2_CMD
| rowspan="2" |CPU.SD2_CMD
| rowspan="2" |W24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_CMD
|-
|ALT5
|GPIO2_IO14
|-
| rowspan="2" |J1.85
| rowspan="2" |SD2_CLK
| rowspan="2" |CPU.SD2_CLK
| rowspan="2" |W23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_CLK
|-
|ALT5
|GPIO2_IO13
|-
|J1.87
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="4" |J1.89
| rowspan="4" |UART3_TXD
| rowspan="4" |CPU.UART3_TXD
| rowspan="4" |D18
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally pulled-up to NVCC_3V3
|ALT0
|UART3_TX
|-
|ALT1
|UART1_RTS_B
(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT2
|USDHC3_VSELECT
|-
|ALT5
|GPIO5_IO27
|-
| rowspan="4" |J1.91
| rowspan="4" |UART3_RXD
| rowspan="4" |CPU.UART3_RXD
| rowspan="4" |E18
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|UART3_RX
|-
|ALT1
|UART1_CTS_B
|-
|ALT2
|USDHC3_RESET_B
|-
|ALT5
|GPIO5_IO26
|-
| rowspan="3" |J1.93
| rowspan="3" |UART1_TXD
| rowspan="3" |CPU.UART1_TXD
| rowspan="3" |F13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|UART1_TX
|-
|ALT1
|ECSPI3_MOSI
|-
|ALT5
|GPIO5_IO23
|-
| rowspan="3" |J1.95
| rowspan="3" |UART1_RXD
| rowspan="3" |CPU.UART1_RXD
| rowspan="3" |E14
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|UART1_RX
|-
|ALT1
|ECSPI3_SCLK
|-
|ALT5
|GPIO5_IO22
|-
| rowspan="2" |J1.97
| rowspan="2" |SD2_WP
| rowspan="2" |CPU.SD2_WP
| rowspan="2" |AA27
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_WP
|-
|ALT5
|GPIO2_IO20
|-
| rowspan="2" |J1.99
| rowspan="2" |SD2_RST_B
| rowspan="2" |CPU.SD2_RESET_B
| rowspan="2" |AB26
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_RESET_B
|-
|ALT5
|GPIO2_IO19
|-
| rowspan="4" |J1.101
| rowspan="4" |I2C2_SCL
| rowspan="4" |CPU.I2C2_SCL
| rowspan="4" |D10
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C2_SCL
|-
|ALT1
|ENET1_1588_EVENT1_IN
|-
|ALT2
|USDHC3_CD_B
(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO5_IO16
|-
| rowspan="4" |J1.103
| rowspan="4" |I2C2_SDA
| rowspan="4" |CPU.I2C2_SDA
| rowspan="4" |D9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|I2C2_SDA
|-
|ALT1
|ENET1_1588_EVENT1_OUT
|-
|ALT2
|USDHC3_WP
(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO5_IO17
|-
| rowspan="6" |J1.105
| rowspan="6" |SAI1_RXD3
| rowspan="6" |CPU.SAI1_RXD3
| rowspan="6" |AF17
| rowspan="6" | NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|SAI1_RX_DATA3
|-
|ALT1
|SAI5_RX_DATA3
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT1)
|-
|ALT3
|PDM_BIT_STREAM3
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT3)
|-
|ALT4
|CORESIGHT_TRACE3
|-
|ALT5
|GPIO4_IO05
|-
|ALT6
|SRC_BOOT_CFG3
|-
| rowspan="5" |J1.107
| rowspan="5" |SAI1_TXD3
| rowspan="5" |CPU.SAI1_TXD3
| rowspan="5" |AF21
| rowspan="5" | NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|SAI1_TX_DATA3
|-
|ALT1
|SAI5_TX_DATA3
|-
|ALT4
|CORESIGHT_TRACE11
|-
|ALT5
|GPIO4_IO15
|-
|ALT6
|SRC_BOOT_CFG11
|-
|J1.109
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="4" |J1.111
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS
| rowspan="4" |AB19
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_SYNC
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)
|-
|ALT1
|SAI5_TX_SYNC
(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|ALT4
|CORESIGHT_EVENTO
|-
|ALT5
|GPIO4_IO10
|-
| rowspan="4" |J1.113
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC
| rowspan="4" |AC18
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_TX_BCLK
(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)
|-
|ALT1
|SAI5_TX_BCLK
(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT4
|CORESIGHT_EVENTI
|-
|ALT5
|GPIO4_IO11
|-
| rowspan="5" |J1.115
| rowspan="5" |SAI1_TXD0
| rowspan="5" |CPU.SAI1_TXD0
| rowspan="5" |AG20
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|SAI1_TX_DATA0
|-
|ALT1
|SAI5_TX_DATA0
|-
|ALT4
|CORESIGHT_TRACE8
|-
|ALT5
|GPIO4_IO12
|-
|ALT6
|SRC_BOOT_CFG8
|-
| rowspan="5" |J1.117
| rowspan="5" |SAI1_TXD1
| rowspan="5" |CPU.SAI1_TXD1
| rowspan="5" |AF20
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|SAI1_TX_DATA1
|-
|ALT1
|SAI5_TX_DATA1
|-
|ALT4
|CORESIGHT_TRACE9
|-
|ALT5
|GPIO4_IO13
|-
|ALT6
|SRC_BOOT_CFG9
|-
| rowspan="5" |J1.119
| rowspan="5" |SAI1_TXD2
| rowspan="5" |CPU.SAI1_TXD2
| rowspan="5" |AG21
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|SAI1_TX_DATA2
|-
|ALT1
|SAI5_TX_DATA2
|-
|ALT4
|CORESIGHT_TRACE10
|-
|ALT5
|GPIO4_IO14
|-
|ALT6
|SRC_BOOT_CFG10
|-
| rowspan="4" |J1.121
| rowspan="4" |SAI1_RXFS
| rowspan="4" |CPU.SAI1_RXFS
| rowspan="4" |AG16
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_SYNC
(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)
|-
|ALT1
|SAI5_RX_SYNC
(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)
|-
|ALT4
|CORESIGHT_TRACE_CLK
|-
|ALT5
|GPIO4_IO00
|-
| rowspan="4" |J1.123
| rowspan="4" |SAI1_RXC
| rowspan="4" |CPU.SAI1_RXC
| rowspan="4" |AF16
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI1_RX_BCLK
|-
|ALT1
|SAI5_RX_BCLK
(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT4
|CORESIGHT_TRACE_CTL
|-
|ALT5
|GPIO4_IO01
|-
| rowspan="7" |J1.125
| rowspan="7" |SAI1_RXD0
| rowspan="7" |CPU.SAI1_RXD0
| rowspan="7" |AG15
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|SAI1_RX_DATA0
|-
|ALT1
|SAI5_RX_DATA0
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)
|-
|ALT2
|SAI1_TX_DATA1
|-
|ALT3
|PDM_BIT_STREAM0
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)
|-
|ALT4
|CORESIGHT_TRACE0
|-
|ALT5
|GPIO4_IO02
|-
|ALT6
|SRC_BOOT_CFG0
|-
| rowspan="6" |J1.127
| rowspan="6" |SAI1_RXD1
| rowspan="6" |CPU.SAI1_RXD1
| rowspan="6" |AF15
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|SAI1_RX_DATA1
|-
|ALT1
|SAI5_RX_DATA1
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)
|-
|ALT3
|PDM_BIT_STREAM1
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)
|-
|ALT4
|CORESIGHT_TRACE1
|-
|ALT5
|GPIO4_IO03
|-
|ALT6
|SRC_BOOT_CFG1
|-
| rowspan="6" |J1.129
| rowspan="6" |SAI1_RXD2
| rowspan="6" |CPU.SAI1_RXD2
| rowspan="6" |AG17
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0
|SAI1_RX_DATA2
|-
|ALT1
|SAI5_RX_DATA2
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)
|-
|ALT3
|PDM_BIT_STREAM2
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)
|-
|ALT4
|CORESIGHT_TRACE2
|-
|ALT5
|GPIO4_IO04
|-
|ALT6
|SRC_BOOT_CFG2
|-
|J1.131
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.133
|LVDS0_CLK_N
|BRIDGE.A_CLKN
|F9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.133
|DSI_CLK_N
|CPU.MIPI_DSI_CLK_N
|A11
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.135
|LVDS0_CLK_P
|BRIDGE.A_CLKP
|F8
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.135
|DSI_CLK_P
|CPU.MIPI_
|B11
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.137
|LVDS0_TX0_N
|BRIDGE.A_Y0N
|C9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.137
|DSI_D0_N
|CPU.MIPI_DSI_D0_N
|A9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.139
|LVDS0_TX0_P
|BRIDGE.A_Y0P
|C8
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.139
|DSI_D0_P
|CPU.MIPI_DSI_D0_P
|B9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.141
|LVDS0_TX1_N
|BRIDGE.A_Y1N
|D9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.141
|DSI_D1_N
|CPU.MIPI_DSI_D1_N
|A10
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.143
|LVDS0_TX1_P
|BRIDGE.A_Y1P
|D8
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.143
|DSI_D1_P
|CPU.MIPI_DSI_D1_P
|B10
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.145
|LVDS0_TX2_N
|BRIDGE.A_Y2N
|E9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.145
|DSI_D2_N
|CPU.MIPI_DSI_D2_N
|A12
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.147
|LVDS0_TX2_P
|BRIDGE.A_Y2P
|E8
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.147
|DSI_D2_P
|CPU.MIPI_DSI_D2_P
|B12
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.149
|LVDS0_TX3_N
|BRIDGE.A_Y3N
|G9
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.149
|DSI_D3_N
|CPU.MIPI_DSI_D3_N
|A13
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.151
|LVDS0_TX3_P
|BRIDGE.A_Y3P
|G8
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.151
|DSI_D3_P
|CPU.MIPI_DSI_D3_P
|B13
| -
|D
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|
|
|-
|J1.153
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|J1.155
|LVDS1_CLK_N
|BRIDGE.B_CLKN
|A6
| -
|D
|
|
|
|-
|J1.157
|LVDS1_CLK_P
|BRIDGE.B_CLKP
|B6
| -
|D
|
|
|
|-
|J1.159
|LVDS1_TX0_N
|BRIDGE.B_Y0N
|A3
| -
|D
|
|
|
|-
|J1.161
|LVDS1_TX0_P
|BRIDGE.B_Y0P
|B3
| -
|D
|
|
|
|-
|J1.163
|LVDS1_TX1_N
|BRIDGE.B_Y1N
|A4
| -
|D
|
|
|
|-
|J1.165
|LVDS1_TX1_P
|BRIDGE.B_Y1P
|B4
| -
|D
|
|
|
|-
|J1.167
|LVDS1_TX2_N
|BRIDGE.B_Y2N
|A5
| -
|D
|
|
|
|-
|J1.169
|LVDS1_TX2_P
|BRIDGE.B_Y2P
|B5
| -
|D
|
|
|
|-
|J1.171
|LVDS1_TX3_N
|BRIDGE.B_Y3N
|A7
| -
|D
|
|
|
|-
|J1.173
|LVDS1_TX3_P
|BRIDGE.B_Y3P
|B7
| -
|D
|
|
|
|-
|J1.175
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="2" |J1.177
| rowspan="2" |SD2_CD_B
| rowspan="2" |CPU.SD2_CD_B
| rowspan="2" |AA26
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
|ALT0
|USDHC2_CD_B
|-
|ALT5
|GPIO2_IO12
|-
| rowspan="3" |J1.179
| rowspan="3" |ECSPI1_SS0
| rowspan="3" |CPU.ECSPI1_SS0
| rowspan="3" |B6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|ECSPI1_SS0
|-
|ALT1
|UART3_RTS_B
(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO5_IO09
|-
| rowspan="3" |J1.181
| rowspan="3" |ECSPI1_SCLK
| rowspan="3" |CPU.ECSPI1_SCLK
| rowspan="3" |D6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|ECSPI1_SCLK
|-
|ALT1
|UART3_RX
|-
|ALT5
|GPIO5_IO06
|-
| rowspan="3" |J1.183
| rowspan="3" |ECSPI1_MISO
| rowspan="3" |CPU.ECSPI1_MISO
| rowspan="3" |A7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|ECSPI1_MISO
|-
|ALT1
|UART3_CTS_B
|-
|ALT5
|GPIO5_IO08
|-
| rowspan="3" |J1.185
| rowspan="3" |GPIO1_IO03
| rowspan="3" |CPU.GPIO1_IO03
| rowspan="3" |AF13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|GPIO1_IO03
|-
|ALT1
|USDHC1_VSELECT
|-
|ALT5
|SDMA1_EXT_EVENT0
|-
| rowspan="3" |J1.187
| rowspan="3" |UART2_TXD
| rowspan="3" |CPU.UART2_TXD
| rowspan="3" |E15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_TX
|-
|ALT1
|ECSPI3_SS0
|-
|ALT5
|GPIO5_IO25
|-
| rowspan="3" |J1.189
| rowspan="3" |UART2_RXD
| rowspan="3" |CPU.UART2_RXD
| rowspan="3" |F15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |used as default Linux console
|ALT0
|UART2_RXD
|-
|ALT1
|ECSPI3_MISO
|-
|ALT5
|GPIO5_IO24
|-
| rowspan="3" |J1.191
| rowspan="3" |UART4_TXD
| rowspan="3" |CPU.UART4_TXD
| rowspan="3" |F18
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|UART4_TX
|-
|ALT1
|UART2_RTS_B
(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO5_IO29
|-
| rowspan="4" |J1.193
| rowspan="4" |UART4_RXD
| rowspan="4" |CPU.UART4_RXD
| rowspan="4" |F19
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|UART4_RX
|-
|ALT1
|UART2_CTS_B
|-
|ALT2
|PCIE1_CLKREQ_B
(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO5_IO28
|-
| rowspan="3" |J1.195
| rowspan="3" |ECSPI1_MOSI
| rowspan="3" |CPU.ECSPI1_MOSI
| rowspan="3" |B7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|ECSPI1_MOSI
|-
|ALT1
|UART3_TX
|-
|ALT5
|GPIO5_IO07
|-
| rowspan="5" |J1.197
| rowspan="5" |GPIO1_IO14
| rowspan="5" |CPU.GPIO1_IO14
| rowspan="5" |AC9
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
|ALT0
|GPIO1_IO14
|-
|ALT1
|USB2_OTG_PWR
|-
|ALT4
|USDHC3_CD_B
(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
|PWM3_OUT
|-
|ALT6
|CCM_CLKO1
|-
| rowspan="3" |J1.199
| rowspan="3" |GPIO1_IO04
| rowspan="3" |CPU.GPIO1_IO04
| rowspan="3" |AG12
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|GPIO1_IO04
|-
|ALT1
|USDHC2_VSELECT
|-
|ALT5
|SDMA1_EXT_EVENT1
|-
| rowspan="3" |J1.201
| rowspan="3" |GPIO1_IO12
| rowspan="3" |CPU.GPIO1_IO12
| rowspan="3" |AB10
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|GPIO1_IO12
|-
|ALT1
|USB1_OTG_PWR
|-
|ALT5
|SDMA2_EXT_EVENT1
|-
|J1.203
|DGND
|DGND
| -
| -
|G
|
|
|
|-
|}
==SODIMM J1 EVEN pins declaration ==
|GPIO5_IO21
|-
| rowspan="34" |J1.76| rowspan="34" |I2C4_SCL| rowspan="34" |CPU.I2C4_SCL| rowspan="34" |D13| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|I2C4_SCL
|ALT1
|PWM2_OUT
|-
|ALT2
|PCIE1_CLKREQ_B
(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|-
|J1.84
|PCIE1_REF_CLKN|CPU.PCIE_REF_CLK_N|A21|VDDA_1V8|D
|
|
|-
|J1.86
|PCIE1_REF_CLKP|CPU.PCIE_REF_CLK_P|B21|VDDA_1V8|D
|
|
|-
|J1.92
|PCIE1_RXN|CPU.PCIE_RXN_N|A19|VDDA_1V8|D
|
|
|-
|J1.94
|PCIE1_RXP|CPU.PCIE_RXN_P|B19|VDDA_1V8|D
|
|
|-
|J1.96
|PCIE1_TXN|CPU.PCIE_TXN_N|A20|VDDA_1V8|D
|
|
|-
|J1.98
|PCIE1_TXP|CPU.PCIE_TXN_P|B20|VDDA_1V8|D
|
|
