Changes

{{InfoBoxBottom}}

<section begin=Body/>

The following paragraphs describe in detail the available PL I/O pins and how they are routed to the BORA Lite connector. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora Lite design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.

Highlighted rows are related to signals that are used for particular functions into the SOM.

N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, '''VDDIO_BANK13 pins must not be left open and must be connected anyway''', either to ground or to an external I/O voltage as described in [[Programmable_logic_(BoraLite)#Introduction | I/O banks table]].

|}

Routing implemented on Bora SoM allows the use of bank 13's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.

|}

The following table reports the available pins connected to bank 34:

|}

Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.

|}

The following table reports the available pins connected to bank 35:

{| class="wikitable" border="1"

|}

Routing implemented on Bora SoM allows the use of bank 35's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.