Changes

The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)|counterpart connectors on BORA Xpress module]].

=== Power supply - JP2 ===

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=== Reset button - S6 ===

<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[:Category:BoraLite |BoraLite]] SOM module

=== WatchDog Settings - S1, S2 and S3 ===

S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.

| WD_SET2 = '0' || OFF || ON

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=== Ethernet port #0 (ETH0) - J8 ===

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=== Ethernet port #1 (ETH1) - J9 ===

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=== BANK's Power GOOD signals - J28 ===

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=== JTAG ===

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=== UART1 - J17 ===

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=== USB OTG - J19 ===

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=== MicroSD - J21 ===

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=== DWM (DAVE Wifi/BT module) socket - J23 ===

J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:

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=== CAN - J24 ===

J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:

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<section begin=Touchscreen/>

<section end=Touchscreen/>

=== LVDS - J26 ===

J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:

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=== FPGA Mezzanine Card (FMC) Connector - J27 ===

J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.

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==== FPGA, WatchDog, RTC, RST - JP22 ====

JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

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==== AUX PINs - JP29 ====

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=== Digilent Pmod™ Compatible headers ===

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===JP27, JP27 and JP28===

These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].