a000298_approval, dave_user
299
edits
Changes
→SODIMM J1 EVEN pins declaration
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| rowspan="43" |J1.58| rowspan="43" |SAI5_MCLK| rowspan="43" |CPU.SAI5_MCLK| rowspan="43" |AD15| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|SAI5_MCLK
(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0)
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|ALT1
|SAI1_TX_BCLK
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|ALT5
|GPIO3_IO25
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| rowspan="42" |J1.60| rowspan="42" |GPIO1_IO15GPIO1_IO10| rowspan="42" |CPU.GPIO1_IO15GPIO1_IO10| rowspan="42" |AD10| rowspan="42" |NVCC_3V3| rowspan="42" |I/O| rowspan="42" |Internally used for ETH PHY interrupt, do not connect
|ALT0
|GPIO1_IO15GPIO1_IO10
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|ALT1
|USB2_OTG_OC|-|ALT5|PWM4_OUT|-|ALT6|CCM_CLKO2USB1_OTG_ID
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| rowspan="3" |J1.62
| rowspan="3" |SAI5_RXFS
| rowspan="3" |CPU.SAI5_RXFS
| rowspan="3" |AB15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|ALT0
|SAI5_RX_SYNC
(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0)
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|ALT1
|GPIO3_IO19
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| rowspan="34" |J1.64| rowspan="34" |SAI5_RXC| rowspan="34" |CPU.SAI5_RXC| rowspan="34" |AC15| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI5_RX_BCLK
(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0)
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|ALT1
|SAI1_TX_DATA1
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|ALT4
|PDM_CLK
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|ALT5
| rowspan="3" |SAI2_TXC
| rowspan="3" |CPU.SAI2_TXC
| rowspan="3" |AD22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |SAI2_TXD0
| rowspan="3" |CPU.SAI2_TXD0
| rowspan="3" |AC22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|GPIO4_IO26
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| rowspan="35" |J1.70| rowspan="35" |SAI2_TXFS| rowspan="35" |CPU.SAI2_TXFS| rowspan="35" |AD23| rowspan="35" |NVCC_3V3| rowspan="35" |I/O| rowspan="35" |
|ALT0
|SAI2_TX_SYNC
|ALT1
|SAI5_TX_DATA1
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|ALT3
|SAI2_TX_DATA1
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|ALT4
|UART1_CTS_B
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|ALT5
|GPIO4_IO24
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| rowspan="34" |J1.72| rowspan="34" |SAI2_RXD0| rowspan="34" |CPU.SAI2_RXD0| rowspan="34" |AC24| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI2_RX_DATA0
|ALT1
|SAI5_TX_DATA0
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|ALT4
|UART1_RTS_B
(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT4)
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|ALT5
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| rowspan="3" |J1.74
| rowspan="3" |SAI5_RXD0I2C4_SDA| rowspan="3" |CPU.SAI5_RXD0I2C4_SDA| rowspan="3" |E13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|SAI5_RX_DATA0 I2C4_SDA
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|ALT1
|SAI1_TX_DATA2PWM1_OUT
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|ALT5
|GPIO3_IO21GPIO5_IO21
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| rowspan="54" |J1.76| rowspan="54" |SAI5_RXD1I2C4_SCL| rowspan="54" |CPU.SAI5_RXD1I2C4_SCL| rowspan="54" |D13| rowspan="54" |NVCC_3V3| rowspan="54" |I/O| rowspan="54" |
|ALT0
|SAI5_RX_DATA1I2C4_SCL
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|ALT1
|SAI1_TX_DATA3PWM2_OUT
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|ALT2
|SAI1_TX_SYNCPCIE1_CLKREQ_B|-|ALT3|SAI5_TX_SYNC(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
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|ALT5
|GPIO3_IO212GPIO5_IO20
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| rowspan="56" |J1.78| rowspan="56" |SAI5_RXD2| rowspan="56" |CPU.SAI5_RXD2| rowspan="56" |AD13| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |
|ALT0
|SAI5_RX_DATA2
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0)
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|ALT1
|ALT2
|SAI1_TX_SYNC
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
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|ALT3
|SAI5_TX_BCLK
(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3)
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|ALT4
|PDM_BIT_STREAM2
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT4)
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|ALT5
|GPIO3_IO23
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| rowspan="56" |J1.80| rowspan="56" |SAI5_RXD3| rowspan="56" |CPU.SAI5_RXD3| rowspan="56" |AC13| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |
|ALT0
|SAI5_RX_DATA3
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0)
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|ALT1
|ALT2
|SAI1_TX_SYNC
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
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|ALT3
|SAI5_TX_DATA0
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|ALT4
|PDM_BIT_STREAM3
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4)
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|ALT5
