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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

3,315 bytes added, 09:15, 22 January 2021
→‎SODIMM J1 ODD pins declaration
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| rowspan="4" |J1.111| rowspan="4" |SAI1_TXFS| rowspan="4" |CPU.SAI1_TXFS|rowspan="4" |AB19| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_TX_SYNC (Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_TX_SYNC(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_EVENTO|-|ALT5|GPIO4_IO10|-| rowspan="4" |J1.113| rowspan="4" |SAI1_TXC| rowspan="4" |CPU.SAI1_TXC| rowspan="4" |AC18| rowspan="4" |NVCC_3V3| rowspan="4" |I/O|rowspan="4" ||ALT0|SAI1_TX_BCLK (Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_TX_BCLK(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_EVENTI
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|J1.113|SAI1_TXC|CPU.SAI1_TXC||NVCC_3V3|I/O||ALT5|GPIO4_IO11
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| rowspan="5" |J1.115| rowspan="5" |SAI1_TXD0| rowspan="5" |CPU.SAI1_TXD0|rowspan="5" |AG20| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_TX_DATA0|-|ALT1|SAI5_TX_DATA0|-|ALT4|CORESIGHT_TRACE8|-|ALT5|GPIO4_IO12|-|ALT6|SRC_BOOT_CFG8
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| rowspan="5" |J1.117| rowspan="5" |SAI1_TXD1| rowspan="5" |CPU.SAI1_TXD1|rowspan="5" |AF20| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_TX_DATA1|-|ALT1|SAI5_TX_DATA1|-|ALT4|CORESIGHT_TRACE9|-|ALT5|GPIO4_IO13|-|ALT6|SRC_BOOT_CFG9
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| rowspan="5" |J1.119| rowspan="5" |SAI1_TXD2| rowspan="5" |CPU.SAI1_TXD2|rowspan="5" |AG21| rowspan="5" |NVCC_3V3| rowspan="5" |I/O| rowspan="5" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_TX_DATA2|-|ALT1|SAI5_TX_DATA2|-|ALT4|CORESIGHT_TRACE10|-|ALT5|GPIO4_IO14|-|ALT6|SRC_BOOT_CFG10|-| rowspan="4" |J1.121| rowspan="4" |SAI1_RXFS| rowspan="4" |CPU.SAI1_RXFS| rowspan="4" |AG16| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_SYNC (Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)|-|ALT1|SAI5_RX_SYNC(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)|-|ALT4|CORESIGHT_TRACE_CLK|-|ALT5|GPIO4_IO00|-| rowspan="4" |J1.123| rowspan="4" |SAI1_RXC| rowspan="4" |CPU.SAI1_RXC| rowspan="4" |AF16| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|SAI1_RX_BCLK|-|ALT1|SAI5_RX_BCLK(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)
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|J1.121|SAI1_RXFS|CPU.SAI1_RXFS||NVCC_3V3|I/O||ALT4|CORESIGHT_TRACE_CTL
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|J1.123|SAI1_RXC|CPU.SAI1_RXC||NVCC_3V3|I/O||ALT5|GPIO4_IO01
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| rowspan="7" |J1.125| rowspan="7" |SAI1_RXD0| rowspan="7" |CPU.SAI1_RXD0|rowspan="7" |AG15| rowspan="7" |NVCC_3V3| rowspan="7" |I/O| rowspan="7" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_RX_DATA0|-|ALT1|SAI5_RX_DATA0(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)|-|ALT2|SAI1_TX_DATA1|-|ALT3|PDM_BIT_STREAM0(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)|-|ALT4|CORESIGHT_TRACE0|-|ALT5|GPIO4_IO02|-|ALT6|SRC_BOOT_CFG0
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| rowspan="6" |J1.127| rowspan="6" |SAI1_RXD1| rowspan="6" |CPU.SAI1_RXD1|rowspan="6" |AF15| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_RX_DATA1|-|ALT1|SAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)|-|ALT3|PDM_BIT_STREAM1(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)|-|ALT4|CORESIGHT_TRACE1|-|ALT5|GPIO4_IO03|-|ALT6|SRC_BOOT_CFG1
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| rowspan="6" |J1.129| rowspan="6" |SAI1_RXD2| rowspan="6" |CPU.SAI1_RXD2|rowspan="6" |AG17| rowspan="6" |NVCC_3V3| rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration:
can be pulled-up or down depending on
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
|ALT0|SAI1_RX_DATA2|-|ALT1|SAI5_RX_DATA2(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)|-|ALT3|PDM_BIT_STREAM2(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)|-|ALT4|CORESIGHT_TRACE2|-|ALT5|GPIO4_IO04|-|ALT6|SRC_BOOT_CFG2
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|J1.131
| rowspan="2" |SD2_CD_B
| rowspan="2" |CPU.SD2_CD_B
| rowspan="2" |AA26
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="3" |ECSPI1_SS0
| rowspan="3" |CPU.ECSPI1_SS0
| rowspan="3" |B6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|ALT1
|UART3_RTS_B
(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
| rowspan="3" |ECSPI1_SCLK
| rowspan="3" |CPU.ECSPI1_SCLK
| rowspan="3" |D6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |ECSPI1_MISO
| rowspan="3" |CPU.ECSPI1_MISO
| rowspan="3" |A7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |GPIO1_IO03
| rowspan="3" |CPU.GPIO1_IO03
| rowspan="3" |AF13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |UART2_TXD
| rowspan="3" |CPU.UART2_TXD
| rowspan="3" |E15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |UART2_RXD
| rowspan="3" |CPU.UART2_RXD
| rowspan="3" |F15
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|-
| rowspan="3" |J1.191
| rowspan="3" |UART1_TXDUART4_TXD| rowspan="3" |CPU.UART1_TXDUART4_TXD| rowspan="3" |F18
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
|ALT0
|UART1_TXUART4_TX
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|ALT1
|ECSPI3_MOSIUART2_RTS_B(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO5_IO23GPIO5_IO29
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| rowspan="34" |J1.193| rowspan="34" |UART1_RXDUART4_RXD| rowspan="34" |CPU.UART1_RXDUART4_RXD| rowspan="34" |F19| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|UART1_RXDUART4_RX
|-
|ALT1
|ECSPI3_SCLKUART2_CTS_B|-|ALT2|PCIE1_CLKREQ_B(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
|-
|ALT5
|GPIO5_IO22GPIO5_IO28
|-
| rowspan="3" |J1.195
U0005
a000298_approval, dave_user
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