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Replaced content with "{{InfoBoxTop}} {{Applies To Diva}} {{InfoBoxBottom}} 300px|frameless|border Please refer to [[Hardware_Manual_%28Diva%29#Pinout_table | section ..."
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{{Applies To Diva}}
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[[File:Diva-front.jpg|300px|frameless|border]]
Please refer to [[File:Diva-front.jpg|200px|frameless|border]] Following table lists pins available on SODIMM-204 edge connector of [[Diva SOM]]. {| class="wikitable" {{table}}| align="center" style="background:#f0f0f0;"|'''Pin'''| align="center" style="background:#f0f0f0;"|'''Pin name'''| align="center" style="background:#f0f0f0;"|'''Internal connection(s)'''| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''| align="center" style="background:#f0f0f0;"|'''Supply group'''| align="center" style="background:#f0f0f0;"|'''Type'''| align="center" style="background:Hardware_Manual_%28Diva%29#f0f0f0;"|'''Voltage'''| align="center" style="background:#f0f0f0;"|'''Notes'''|-| 1||DGND|||||||||||||-| 2||AM335X_GPMC_WPn||CPU.[GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MII1_TXEN/UART4_TXD/GPIO0_31]||U17|||||||||-| 3||AM335X_I2C0_SCL||CPU.[I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6]||C16|||||||||-| 4||AM335X_GPMC_CS0n||CPU.[GPMC_CSN0///////GPIO1_29]||V6|||||||||-| 5||AM335X_I2C0_SDA||CPU.[I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5]||C17|||||||||-Pinout_table | section 6||AM335X_GPMC_CS1n||CPU.[GPMC_CSN1/GPMC_CLK/MMC1_CLK/PR1_EDIO_DATA_IN6/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30]||U9|||||||||-| 7||WD_SET0|||||||||||||-| 8||AM335X_GPMC_CS2n||CPU.[GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31]||V9|||||||||-| 9||WD_SET1|||||||||||||-| 10||AM335X_GPMC_CS3n||CPU.[GPMC_CSN3///MMC2_CMD/PR1_MII0_CRS/PR1_MDIO_DATA/EMU4/GPIO2_0]||T13|||||||||-| 11||WD_SET2|||||||||||||-| 12||DGND|||||||||||||-| 13||EEPROM_WP|||||||||||||-| 14||AM335X_GPMC_CLK||CPU.[GPMC_CLK/LCD_MEMORY_CLK/GPMC_WAIT1/MMC2_CLK/PR1_MII1_CRS/PR1_MDIO_MDCLK/MCASP0_FSR/GPIO2_1]||V12|||||||||-| 15||EEPROM_A1|||||||||||||-| 16||AM335X_GPMC_WEn||CPU.[GPMC_WEN//TIMER6/////GPIO2_4]||U6|||||||||-| 17||EEPROM_A0|||||||||||||-| 18||AM335X_GPMC_OEn_REn||CPU.[GPMC_OEN_REN//TIMER6/////GPIO2_4]||T7|||||||||-| 19||AM335X_EXT_WAKEUP||CPU.EXT_WAKEUP||C5|||||||||-| 20||AM335X_GPMC_ADVn_ALE||CPU.[GPMC_ADVN_ALE//TIMER4/////GPIO2_2]||R7|||||||||-| 21||DGND|||||||||||||-| 22||AM335X_GPMC_BE0n_CLE||CPU.[GPMC_BE0N_CLE//TIMER5/////GPIO2_5]||T6|||||||||-| 23||AM335X_RMII1_REFCLK||||H18|||||||||-| 24||AM335X_GPMC_BE1n||CPU.[GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28]||U18|||||||||-| 25||AM335X_UART0_TXD||CPU.[UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11]||E16|||||||||-| 26||AM335X_GPMC_WAIT||CPU.[GPMC_WAIT0/GMII2_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_COL/UART4_RXD/GPIO0_30]||T17|||||||||-| 27||AM335X_UART0_RXD||CPU.[UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10]||E15|||||||||-| 28||AM335X_GPMC_A0||CPU.[GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16]||R13|||||||||-| 29||AM335X_UART0_RTSn||CPU.[UART0_RTSN/UART4_TXD/DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO1_9]||E17|||||||||-| 30||AM335X_GPMC_A1||CPU.[GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM0_SYNCO/GPIO1_17]||V14|||||||||-| 31||AM335X_UART0_CTSn||CPU.[UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8]||E18|||||||||-| 32||DGND|||||||||||||-| 33||AM335X_UART1_TXD||CPU.[UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15]||D15|||||||||-| 34||AM335X_GPMC_A2||CPU.[GPMC_A2/GMII2_TXD3/RGMII2_TD3/MMC2_DAT1/GPMC_A18/PR1_MII1_TXD2/EHRPWM1A/GPIO1_18]||U14|||||||||-| 35||AM335X_UART1_RXD||CPU.[UART1_RXD/MMC1_SDWP/DCAN1_TX/I2C1_SDA//PR1_UART0_RXD/PR1_PRU1_PRU_R31_16/GPIO0_14]||D16|||||||||-| 36||AM335X_GPMC_A3||CPU.[GPMC_A3/GMII2_TXD2/RGMII2_TD2/MMC2_DAT2/GPMC_A19/PR1_MII1_TXD1/EHRPWM1B/GPIO1_19]||T14|||||||||-| 37||AM335X_UART1_RTSn||CPU.[UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13]||D17|||||||||-| 38||AM335X_GPMC_A4||CPU.[GPMC_A4/GMII2_TXD1/RGMII2_TD1/RMII2_TXD1/GPMC_A20/PR1_MII1_TXD0/EQEP1A_IN/GPIO1_20]||R14|||||||||-| 39||AM335X_UART1_CTSn||CPU.[UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12]||D18|||||||||-| 40||AM335X_GPMC_A5||CPU.[GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21]||V15|||||||||-| 41||DGND|||||||||||||-| 42||AM335X_GPMC_A6||CPU.[GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22]||U15|||||||||-| 43||AM335X_SPI0_SCLK||CPU.[SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2]||A17|||||||||-| 44||AM335X_GPMC_A7||CPU.[GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23]||T15|||||||||-| 45||AM335X_SPI0_D0||CPU.[SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3]||B17|||||||||-| 46||AM335X_GPMC_A8||CPU.[GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24]||V16|||||||||-| 47||AM335X_SPI0_D1||CPU.[SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4]||B16|||||||||-| 48||AM335X_GPMC_A9||CPU.[GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25]||U16|||||||||-| 49||AM335X_SPI0_CS0||CPU.[SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5]||A16|||||||||-| 50||AM335X_GPMC_A10||CPU.[GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_RXDV/MCASP0_AXR0/GPIO1_26]||T16|||||||||-| 51||AM335X_SPI0_CS1||CPU.[SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6]||C15|||||||||-| 52||DGND|||||||||||||-| 53||USB0_CE||CPU.USB0_CE||M15|||||||||-| 54||AM335X_GPMC_A11||CPU.[GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27]||V17|||||||||-| 55||USB0_ID||CPU.USB0_ID||P16|||||||||-| 56||AM335X_GPMC_AD0||CPU.[GPMC_AD0/MMC1_DAT0//////GPIO1_0]||U7|||||||||-| 57||USB0_DP||CPU.USB0_DP||N17|||||||||-| 58||AM335X_GPMC_AD1||CPU.[GPMC_AD1/MMC1_DAT1//////GPIO1_1]||V7|||||||||-| 59||USB0_DM||CPU.USB0_DM||N18|||||||||-| 60||AM335X_GPMC_AD2||CPU.[GPMC_AD2/MMC1_DAT2//////GPIO1_2]||R8|||||||||-| 61||DGND|||||||||||||-| 62||AM335X_GPMC_AD3||CPU.[GPMC_AD3/MMC1_DAT3//////GPIO1_3]||T8|||||||||-| 63||USB0_DRVVBUS||CPU.USB0_DRVVBUS||F16|||||||||-| 64||AM335X_GPMC_AD4||CPU.[GPMC_AD4/MMC1_DAT4//////GPIO1_4]||U8|||||||||-| 65||VUSB_VBUS0||CPU.USB0_VBUS||P15|||||||||-| 66||AM335X_GPMC_AD5||CPU.[GPMC_AD5/MMC1_DAT5//////GPIO1_5]||V8|||||||||-| 67||AM335x_EXTINTn||CPU.NMIn||B18|||||||||-| 68||AM335X_GPMC_AD6||CPU.[GPMC_AD6/MMC1_DAT6//////GPIO1_6]||R9|||||||||-| 69||AM335X_XDMA_EVENT_INTR0||CPU.[XDMA_EVENT_INTR0//TIMER4/CLKOUT1/SPI1_CS1/PR1_PRU1_PRU_R31_16/EMU2/GPIO0_19]||A15|||||||||-| 70||AM335X_GPMC_AD7||CPU.[GPMC_AD7/MMC1_DAT7//////GPIO1_7]||T9|||||||||-| 71||AM335X_XDMA_EVENT_INTR1||CPU.[XDMA_EVENT_INTR1//TCLKIN/CLKOUT2/TIMER7/PR1_PRU0_PRU_R31_16/EMU3/GPIO0_20]||D14|||||||||-| 72||DGND|||||||||||||-| 73||USB1_CE||CPU.USB1_CE||P18|||||||||-| 74||AM335X_GPMC_AD8||CPU.[GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22]||U10|||||||||-| 75||USB1_ID||CPU.USB1_ID||P17|||||||||-| 76||AM335X_GPMC_AD9||CPU.[GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_COL//GPIO0_23]||T10|||||||||-| 77||USB1_DP||CPU.USB1_DP||R17|||||||||-| 78||AM335X_GPMC_AD10||CPU.[GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26]||T11|||||||||-| 79||USB1_DM||CPU.USB1_DM||R18|||||||||-| 80||AM335X_GPMC_AD11||CPU.[GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCO/PR1_MII0_TXD3//GPIO0_27]||U12|||||||||-| 81||DGND|||||||||||||-| 82||AM335X_GPMC_AD12||CPU.[GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12]||T12|||||||||-| 83||USB1_DRVVBUS||CPU.USB1_DRVVBUS||F15|||||||||-| 84||AM335X_GPMC_AD13||CPU.[GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13]||R12|||||||||-| 85||VUSB_VBUS1||CPU.USB1_VBUS||T18|||||||||-| 86||AM335X_GPMC_AD14||CPU.[GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14]||V13|||||||||-| 87||AM335X_AIN0||CPU.AIN0||B6|||||||||-| 88||AM335X_GPMC_AD15||CPU.[GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15]||U13|||||||||-| 89||AM335X_AIN1||CPU.AIN1||C7|||||||||-| 90||AM335X_LCD_PCLK||CPU.[LCD_PCLK/GPMC_A10/PR1_MII0_CRS/PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24]||V5|||||||||-| 91||AM335X_AIN2||CPU.AIN2||B7|||||||||-| 92||DGND|||||||||||||-| 93||AGND_TSC|||||||||||||-| 94||AM335X_LCD_VSYNC||CPU.[LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22]||U5|||||||||-| 95||AM335X_AIN3||CPU.AIN3||A7|||||||||-| 96||AM335X_LCD_HSYNC||CPU.[LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23]||R5|||||||||-| 97||AM335X_AIN4||CPU.AIN4||C8|||||||||-| 98||AM335X_LCD_AC_BIAS_EN||CPU.[LCD_AC_BIAS_EN/GPMC_A11/PR1_MII1_CRS/PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25]||R6|||||||||-| 99||AM335X_AIN5||CPU.AIN5||B8|||||||||-| 100||AM335X_LCD_DATA0||CPU.[LCD_DATA0/GPMC_A0/PR1_MII_MT0_CLK/EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6]||R1|||||||||-| 101||AGND_TSC|||||||||||||-| 102||AM335X_LCD_DATA1||CPU.[LCD_DATA1/GPMC_A1/PR1_MII0_TXEN/EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7]||R2|||||||||-| 103||AM335X_AIN6||CPU.AIN6||A8|||||||||-| 104||AM335X_LCD_DATA2||CPU.[LCD_DATA2/GPMC_A2/PR1_MII0_TXD3/EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8]||R3|||||||||-| 105||AM335X_AIN7||CPU.AIN7||C9|||||||||-| 106||AM335X_LCD_DATA3||CPU.[LCD_DATA3/GPMC_A3/PR1_MII0_TXD2/EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9]||R4|||||||||-| 107||AGND_TSC|||||||||||||-| 108||AM335X_LCD_DATA4||CPU.[LCD_DATA4/GPMC_A4/PR1_MII0_TXD1/EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10]||T1|||||||||-| 109||AM335X_ECAP0_IN_PWM0_OUT||CPU.[ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7]||C18|||||||||-| 110||AM335X_LCD_DATA5||CPU.[LCD_DATA5/GPMC_A5/PR1_MII0_TXD0/EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11]||T2|||||||||-| 111||AM335X_MMC_D3||CPU.[MMC0_DAT3/GPMC_A20/UART4_CTSN/TIMER5/UART1_DCDN/PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_8/GPIO2_26]||F17|||||||||-| 112||DGND|||||||||||||-| 113||AM335X_MMC_D2||CPU.[MMC0_DAT2/GPMC_A21/UART4_RTSN/TIMER6/UART1_DSRN/PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_9/GPIO2_27]||F18|||||||||-| 114||AM335X_LCD_DATA6||CPU.[LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12]||T3|||||||||-| 115||AM335X_MMC_D1||CPU.[MMC0_DAT1/GPMC_A22/UART5_CTSN/UART3_RXD/UART1_DTRN/PR1_PRU0_PRU_R30_10/PR1_PRU0_PRU_R31_10/GPIO2_28]||G15|||||||||-| 116||AM335X_LCD_DATA7||CPU.[LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13]||T4|||||||||-| 117||AM335X_MMC_D0||CPU.[MMC0_DAT0/GPMC_A23/UART5_RTSN/UART3_TXD/UART1_RIN/PR1_PRU0_PRU_R30_11/PR1_PRU0_PRU_R31_11/GPIO2_29]||G16|||||||||-| 118||AM335X_LCD_DATA8||CPU.[LCD_DATA8/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14]||U1|||||||||-| 119||AM335X_MMC_CMD||CPU.[MMC0_CMD/GPMC_A25/UART3_RTSN/UART2_TXD/DCAN1_RX/PR1_PRU0_PRU_R30_13/PR1_PRU0_PRU_R31_13/GPIO2_31]||G18|||||||||-| 120||AM335X_LCD_DATA9||CPU.[LCD_DATA9/GPMC_A13/EHRPWM1_SYNCO/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15]||U2|||||||||-| 121||DGND|||||||||||||-| 122||AM335X_LCD_DATA10||CPU.[LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16]||U3|||||||||-| 123||AM335X_MMC_CLK||CPU.[MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30]||G17|||||||||-| 124||AM335X_LCD_DATA11||CPU.[LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17]||U4|||||||||-| 125||JTAG_EMU1||CPU.[EMU1///////GPIO3_8]||B14|||||||||-| 126||AM335X_LCD_DATA12||CPU.[LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8]||V2|||||||||-| 127||JTAG_EMU0||CPU.[EMU0///////GPIO3_7]||C14|||||||||-| 128||AM335X_LCD_DATA13||CPU.[LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9]||V3|||||||||-| 129||JTAG_TDO||CPU.TDO||A11|||||||||-| 130||AM335X_LCD_DATA14||CPU.[LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10]||V4|||||||||-| 131||JTAG_TDI||CPU.TDI||B11|||||||||-| 132||DGND|||||||||||||-| 133||JTAG_TMS||CPU.TMS||C11|||||||||-| 134||AM335X_LCD_DATA15||CPU.[LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11]||T5|||||||||-| 135||JTAG_TRSTn||CPU.TRSTn||B10|||||||||-| 136||AM335X_MCASP0_FSR||CPU.[MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19]||C13|||||||||-| 137||JTAG_TCK||CPU.TCK||A12|||||||||-| 138||AM335X_MCASP0_AXR1||CPU.[MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20]||D13|||||||||-| 139||ETH_CTTD|||||||||||||-| 140||AM335X_MCASP0_FSX||CPU.[MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15]||B13|||||||||-| 141||DGND|||||||||||||-| 142||AM335X_MCASP0_AXR0||CPU.[MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16]||D12|||||||||-| 143||ETH_CTRD|||||||||||||-| 144||AM335X_MCASP0_AHCLKR||CPU.[MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17]||C12|||||||||-| 145||ETH_TX-||ETHPHY.TXN||28|||||||||-| 146||AM335X_MCASP0_ACLKR||CPU.[MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18]||B12|||||||||-| 147||ETH_TX+||ETHPHY.TXP||29|||||||||-| 148||AM335X_MCASP0_AHCLKX||CPU.[MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21]||A14|||||||||-| 149||ETH_RX-||ETHPHY.RXN||30|||||||||-| 150||AM335X_MCASP0_ACLKX||CPU.[MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14]||A13|||||||||-| 151||ETH_RX+||ETHPHY.RXP||31|||||||||-| 152||DGND|||||||||||||-| 153||EMAC0_PHY_LED_SPEED||ETHPHY.LED2/nINTSEL||2||||||||10kOhm pull-down|-| 154||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 155||EMAC0_PHY_LED_LINK/ACT||ETHPHY.LED1/nREGOFF||3|||||||||-| 156||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by of the Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 157||AM335X_GMII1_TXD3||CPU.[GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16Hardware Manual]||J18|||||||||-| 158||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 159||AM335X_GMII1_TXD2||CPU.[GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17]||K15|||||||||-| 160||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 161||DGND|||||||||||||-| 162||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 163||AM335X_GMII1_RXDV||CPU.[GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4]||J17|||||||||-| 164||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 165||AM335X_GMII1_MDIO_CLK||CPU.[MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1]||M18|||||||||-| 166||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 167||AM335X_GMII1_MDIO_DATA||CPU.[MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0]||M17|||||||||-| 168||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 169||AM335X_GMII1_COL||CPU.[GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0]||H16|||||||||-| 170||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 171||AM335X_GMII1_RXD3||CPU.[GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18]||L17|||||||||-| 172||DGND|||||||||||||-| 173||AM335X_GMII1_RXD2||CPU.[GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19]||L16|||||||||-| 174||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 175||AM335X_GMII1_RXCLK||CPU.[GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10]||L18|||||||||-| 176||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 177||AM335X_GMII1_TXCLK||CPU.[GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9]||K18|||||||||-| 178||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 179||PMIC_CLK32OUT||PMIC.CLK32KOUT||PMIC.38|||||||||-| 180||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 181||DGND|||||||||||||-| 182||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 183||PMIC_PWR_EN||CPU.PMIC_PWR_EN, PMIC.PWRHOLD||CPU.C6, PMIC.1|||||||||-| 184||NC/Voltage monitoring||||||||||||By default this pin must not be connected. Optionally it can route power voltage generated by Diva PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.|-| 185||PMIC_INT1||PMIC.INT1||45|||||||||-| 186||VIN|||||||||||||-| 187||PMIC_SLEEP||PMIC.SLEEP||37|||||||||-| 188||VIN|||||||||||||-| 189||PMIC_PWRON|||||||||||||-| 190||VIN|||||||||||||-| 191||PMIC_nRESPWRON|||||||||||||-| 192||DGND|||||||||||||-| 193||MRSTn|||||||||||||-| 194||VIN|||||||||||||-| 195||RTC_PWRONRSTn||CPU.RTC_PWRONRSTn||B5|||||||||-| 196||VIN|||||||||||||-| 197||WARMRSTn|||||||||||||-| 198||VIN|||||||||||||-| 199||PORSTn|||||||||||||-| 200||VIN|||||||||||||-| 201||DGND|||||||||||||-| 202||VIN|||||||||||||-| 203||PMIC_VBACKUP||PMIC.VBACKUP||27|||||||||-| 204||VIN|||||||||||||-| |}
