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Created page with "===Default boot sequence=== DM8148 provides several boot sequences selectable via BTMODE[4:0] bootstrap pins. By default, Naon provides the following configuration: * BTMODE[1..."
===Default boot sequence===
DM8148 provides several boot sequences selectable via BTMODE[4:0] bootstrap pins. By default, Naon provides the following configuration:
* BTMODE[15]: 0
* BTMODE[14:13]: 10
* BTMODE[12]: 1
* BTMODE[11]: 0
* BTMODE[10]: 0
* BTMODE[9:8]: 01
* BTMODE[7:5]: 000
* BTMODE[4:0]: 10111.
Thus default boot sequence is:
# MMC
# SPI
# UART
# EMAC.
===Boot sequence options===
Please note that this sequence can be changed by optional [[#Boot sequence_2 |external circuitry implemented on carrier board]]. Assuming default configuration is not changed and no boot MMC card is connected to processor's MMC1 interface, the actual boot sequence performed by ARM core will be:
# bootrom: this is executed from internal ROM code memory
# U-Boot bootloader (1st stage)
#* copied from on-board NOR flash memory connected to SPI0 port to on-chip SRAM by bootrom
#* executed from on-chip SRAM
# U-Boot bootloader (2nd stage)
#* copied by U-Boot 1st stage from NOR flash memory connected to SPI0 port to SDRAM
#* executed from SDRAM.
DM8148 provides several boot sequences selectable via BTMODE[4:0] bootstrap pins. By default, Naon provides the following configuration:
* BTMODE[15]: 0
* BTMODE[14:13]: 10
* BTMODE[12]: 1
* BTMODE[11]: 0
* BTMODE[10]: 0
* BTMODE[9:8]: 01
* BTMODE[7:5]: 000
* BTMODE[4:0]: 10111.
Thus default boot sequence is:
# MMC
# SPI
# UART
# EMAC.
===Boot sequence options===
Please note that this sequence can be changed by optional [[#Boot sequence_2 |external circuitry implemented on carrier board]]. Assuming default configuration is not changed and no boot MMC card is connected to processor's MMC1 interface, the actual boot sequence performed by ARM core will be:
# bootrom: this is executed from internal ROM code memory
# U-Boot bootloader (1st stage)
#* copied from on-board NOR flash memory connected to SPI0 port to on-chip SRAM by bootrom
#* executed from on-chip SRAM
# U-Boot bootloader (2nd stage)
#* copied by U-Boot 1st stage from NOR flash memory connected to SPI0 port to SDRAM
#* executed from SDRAM.