Changes

<section begin="History" />

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<section end="History" /><section begin="Body" />

Two options are available related to system The default primary boot. They are identified device is internally set by pull-up or pull-down resistors according to the Boot field Mode fileld of the ordering code as follows:* 0: SPI NOR / SD option (SOM code: DXLxxxx0xxR)* 1: NAND / SD option (SOM code: DXLxxxx1xxR)For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.

In any case, boot process is managed by The BOOT_MODEx signals are also present on-chip the SoM connector to override the primary boot ROM code that is described in detail in processor's Reference Manualdevice.

=== SPI NOR / SD option ===Selection of primary boot device is determined by The following table shows all the BOOT_MODE_SEL signal as followsavailable options:* BOOT_MODE_SEL = 0** primary boot device is SD1* boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically* BOOT_MODE_SEL = 1 or floating** primary boot device is SPI NOR flash connected to eCSPI1** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically

=== NAND / SD option ===Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows[[File:* BOOT_MODE_SEL = 0** primary boot device is SD1** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL = 1 or floating** primary boot device is NAND flash** in case no valid image is found in NAND flash, STM32MP1 boot ROM shall enable USB serial download mode automaticallymodes.png | 800px]]

===Important note for DualLite/Solo based products (''manufacture mode'' management)===When Dual Lite Use 1k resistors either to VDD or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order DGND to prevent drive the intervention of bootrom's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement [[Reset_scheme_(AxelLite)#Handling_CPU-initiated_software_reset|software reset circuit]], it is high during bootstrap stage by designBOOT_MODEx signals.