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Created page with "<section begin=History/> {| style="border-collapse:collapse; " ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |- ! style="borde..."
<section begin=History/>
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Sep 2020
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
|-
|}
<section end=History/>
__FORCETOC__
<section begin=Body/>
== Power Supply Unit (PSU) and recommended power-up sequence ==
Implementing correct power-up sequence for ''iMX8M Mini'' processors is not a trivial task because several power rails are involved.
MITO 8M Mini SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
[[File:MITO 8M-power-sequence.png | 800px]]
The PSU is composed of two main blocks:
* power management integrated circuit
* additional generic power management circuitry that completes PMIC functionalities
The PSU:
* generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
* synchronizes the powering up of carrier board in order to prevent back power
=== Power-up sequence===
The typical power-up sequence is the following:
# 3.3VIN main power supply rail is powered
# SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason)
# CPU_PORn (active-low) is driven low by PMIC
# RTC_RESET_B are internally released after 200ms
# VDD_SOC regulator starts and enables the VDD_ARM and PMIC regulators
# PMIC initiates power-up sequence needed by iMX8M processor
# BOARD_PGOOD goes up when NVCC_3V3 (CPU I/O power rail) is ready
# CPU_PORn is deasserted after the last regulator to bring the processor out of reset
==== Note on BOARD_PGOOD usage ====
BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.
Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly because it has a 20mA output current absolute maximum rating.
In these cases a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution.
[[File:MITO 8M-power-good.png]]
Additionally, we suggest using an IC with Schmitt trigger input ports.
----
[[Category:MITO 8M Mini]]
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Sep 2020
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
|-
|}
<section end=History/>
__FORCETOC__
<section begin=Body/>
== Power Supply Unit (PSU) and recommended power-up sequence ==
Implementing correct power-up sequence for ''iMX8M Mini'' processors is not a trivial task because several power rails are involved.
MITO 8M Mini SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
[[File:MITO 8M-power-sequence.png | 800px]]
The PSU is composed of two main blocks:
* power management integrated circuit
* additional generic power management circuitry that completes PMIC functionalities
The PSU:
* generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
* synchronizes the powering up of carrier board in order to prevent back power
=== Power-up sequence===
The typical power-up sequence is the following:
# 3.3VIN main power supply rail is powered
# SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason)
# CPU_PORn (active-low) is driven low by PMIC
# RTC_RESET_B are internally released after 200ms
# VDD_SOC regulator starts and enables the VDD_ARM and PMIC regulators
# PMIC initiates power-up sequence needed by iMX8M processor
# BOARD_PGOOD goes up when NVCC_3V3 (CPU I/O power rail) is ready
# CPU_PORn is deasserted after the last regulator to bring the processor out of reset
==== Note on BOARD_PGOOD usage ====
BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.
Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly because it has a 20mA output current absolute maximum rating.
In these cases a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution.
[[File:MITO 8M-power-good.png]]
Additionally, we suggest using an IC with Schmitt trigger input ports.
----
[[Category:MITO 8M Mini]]