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Video input ports (Naon)

203 bytes added, 14:15, 9 August 2012
Routing on Naon connectors
===Routing on Naon connectors===
The following tables summarizes lists which signals - referred to video input/output ports - are routed to Naon connectors and thus are available to user application. It is also useful to visualize potential issues due to the pads' multiplexing scheme.
{| class="wikitable" {{table}}
| align="center" style="background:#f0f0f0;"|'''PAD'''
| P26||||||B_CLK||||AVID||||||Y
|-
| Y22||||||A_CLK||||||||||NY
|-
| AE27||||||A_D23||||R_CR[2]||HPDET||||Y
| L24||||||B_D0||||||||||Y
|-
| AE24||||||A_HSYNC||||CLK||||||NY
|-
| AC24||||||A_VSYNC||||HSYNC||||||Y
|
|}
Following is a brief summary of input ports available on Naon connectors:
* VIN0A: fully available (24/16/8-bit)
* VIN0B: fully available (8-bit)
* VIN1A: not available
 
* CPI: fully available (up to 16-bit)
===Related links===
[[VIN0 to HDMI latency measurement (Naon)]]

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