dave_user
207
edits
Changes
no edit summary
* The inference was repeated several times and the average execution time was computed
* All the files required to run the test—the executable, the image files, etc.—are stored on a tmpfs RAM disk in order to make file system/storage medium overhead neglectable.
'''dexplorer''' status DPU
<pre>
root@xilinx-zcu104-2020_1:~# dexplorer -v -w
Vitis AI for Edge DPU version 1.2
Copyright 2019 Xilinx Inc.
DExplorer version 3.0
Build Label: Jun 19 2020 05:21:20
DSight version 2.1
Build Label: Jun 19 2020 05:21:20
DDump version 2.0
Build Label: Jun 19 2020 05:21:20
N2Cube Core library version 4.2
Build Label: Jun 19 2020 05:21:16
[DPU IP Spec]
IP Timestamp : 2020-06-18 12:00:00
DPU Core Count : 2
[DPU Core Configuration List]
DPU Core : #0
DPU Enabled : Yes
DPU Arch : B4096
DPU Target Version : v1.4.1
DPU Freqency : 300 MHz
Ram Usage : High
DepthwiseConv : Enabled
DepthwiseConv+Relu6 : Enabled
Conv+Leakyrelu : Enabled
Conv+Relu6 : Enabled
Channel Augmentation : Enabled
Average Pool : Enabled
DPU Core : #1
DPU Enabled : Yes
DPU Arch : B4096
DPU Target Version : v1.4.1
DPU Freqency : 300 MHz
Ram Usage : High
DepthwiseConv : Enabled
DepthwiseConv+Relu6 : Enabled
Conv+Leakyrelu : Enabled
Conv+Relu6 : Enabled
Channel Augmentation : Enabled
Average Pool : Enabled
</pre>
'''ddump'''
root@xilinx-zcu104-2020_1:~/VART_2# ddump -f bin/dpu_custom_cnn_0.elf -a
DPU Kernel List from file bin/dpu_custom_cnn_0.elf
ID: Name
0: custom_cnn_0
DPU Kernel name: custom_cnn_0
----------------------------------------------------------------
-> DPU Kernel general info
Mode: NORMAL
Code Size: 0.02MB
Param Size: 4.60MB
Workload MACs: 498.209MOP
IO Memory Space: 0.52MB
Mean Value: 0, 0, 0
Node Count: 6
Tensor Count: 7
Tensor In(H*W*C)
Tensor ID-0: 224*224*3
Tensor Out(H*W*C)
Tensor ID-6: 1*1*6
-> DPU architecture info
DPU ABI Ver: v2.1
DPU Configuration Parameters
DPU Target Ver: 1.4.1
DPU Arch Type: B4096
RAM Usage: high
DepthwiseConv: Enabled
DepthwiseConv+Relu6: Enabled
Conv+Leakyrelu: Enabled
Conv+Relu6: Enabled
Channel Augmentation: Enabled
Average Pool: Enabled
-> DNNC compiler info
DNNC Ver: VAI_C Compiler for Edge, Version v5.01
DPU Target : v1.4.1
Build Label: Jun 23 2020 03:34:14
Copyright @2020 Xilinx Inc. All Rights Reserved.
'''Dsight''' per DNNDK
<pre>
</pre>
'''vaitrace''' + ''' vaiProfiler''' per VART
<pre>
JSON
</pre>
