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=== Description ===
The i.MX6 processor provides SSI Synchronous Serial Interface port that allow to communicate with audio codecs that implement the inter-IC sound busstandard bus standard (I2S).
The SSI has independent transmitter includes the following features: * Independent (asynchronous) or shared (synchronous) transmit and receiver receive sections with separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode* Normal mode operation using frame sync* 2 sets of Transmit and Receive FIFOs. Each of the four FIFOs is 15x32 bits. The two sets of Tx/Rx FIFOs can be used in Network mode to provide 2 independent channels for transmission and reception (this mode is named as two-channel mode in the following descriptions)* Programmable data interface modes such as I2S, LSB, MSB aligned* Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)* Programmable I2S modes (Master, Slave or Normal). Maximum audio sampling rate is 196kHz. (Note that maximum sampling rate depends on IPG frequency). Minimum audio sampling rate is 8kHz. Network clock (as an oversampling clock generation and to external device) available as output from SRCK in I2S Master mode* AC97 support. Max frame synchronizationrate is 48kHz.Min frame rate is 8kHz
The processor also provides standard Sony/Philips Digital Interface (SPDIF) stereo transceiver that allows the processor to receive and transmit digital audio.
