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MITO 8M SOM/MITO 8M Hardware/Pinout Table

14,059 bytes added, 10:47, 29 September 2020
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Reverted edits by U0009 (talk) to last revision by U0005
<section end=History/>
<section begin=Body/>
==Pinout Table=====Introduction===
This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.
Each row in the pinout tables contains the following information:
{| class="wikitable" style="width:50%;"
|-
|'''Pin'''
| Reference to the connector pin
|-
|'''Pin Name'''
| Pin (signal) name on the AxelLite connectors
|-
|'''Internal<br>connections'''
| Connections to the Axel Ultra components
* CPU.<x> : pin connected to CPU pad named <x>
* PMIC.<x> : pin connected to the Power Manager IC
* LAN.<x> : pin connected to the LAN PHY
* BRIDGE.<x> : pin connected to the MIPI-to-LVDS bridge
* SV.<x>: pin connected to voltage supervisor
|-
|'''Ball/pin #'''
| Component ball/pin number connected to signal
|-
|'''Voltage''' || I/O voltage levels
|-
|'''Type'''
| Pin type:
* I = Input
* O = Output
* D = Differential
* Z = High impedance
* S = Power supply voltage
* G = Ground
* A = Analog signal
|-
|'''Notes'''
|Remarks on special pin characteristics
|-
|'''Pin MUX alternative functions'''
|Muxes:
* Pin ALT-0
* Pin ALT-1
* Pin ALT-2
* Pin ALT-3
* Pin ALT-4
* Pin ALT-5
* Pin ALT-6
* Pin ALT-7
* Pin ALT-8
|-
|}
===Pinout Table ODD pins declaration ===
==Pinout Table ODD pins declaration==
{| class="wikitable"
! latexfontsize="scriptsize" | APin ! latexfontsize="scriptsize" | BPin Name! latexfontsize="scriptsize" | CInternal Connections ! latexfontsize="scriptsize" | DBall/pin # ! latexfontsize="scriptsize" | E<nowiki>Voltage|domain</nowiki>! latexfontsize="scriptsize" | FType ! latexfontsize="scriptsize" | GNotes! colspan="2" latexfontsize="scriptsize" | HAlternative Functions|-|J1.1|DGND|DGND| -|<nowiki>-</nowiki>|G||||-|J1.3|3.3VIN|INPUT VOLTAGE| -|3.3VIN|S||||-|J1.5|3.3VIN|INPUT VOLTAGE| -|3.3VIN|S||||-|J1.7|3.3VIN|INPUT VOLTAGE| -|3.3VIN|S||||-|J1.9|3.3VIN|INPUT VOLTAGE| -|3.3VIN|S||||-|J1.11|DGND|DGND| -| -|G||||-|J1.13|ETH0_LED1|LAN.LED1/PME_N1|17|NVCC_1V8|I/O|Must be level translated if used @ 3V3|||-|J1.15|ETH0_LED2|LAN.LED2|15|NVCC_1V8|I/O|Must be level translated if used @ 3V3|||-|J1.17|DGND|DGND| -| -|G||||-|J1.19|ETH0_TXRX0_P|LAN.TXRXP_A|2| -|D||||-|J1.21|ETH0_TXRX0_M|LAN.TXRXM_A|3| -|D||||-|J1.23|ETH0_TXRX1_P|LAN.TXRXP_B|5| -|D||||-|J1.25|ETH0_TXRX1_M|LAN.TXRXM_B|6| -|D||||-|J1.27|ETH0_TXRX2_P|LAN.TXRXP_C|7| -|D||||-|J1.29|ETH0_TXRX2_M|LAN.TXRXM_C|8| -|D|||
|-
|AJ1.31|AETH0_TXRX3_P|ALAN.TXRXP_D|A10|A-|AD||||-|J1.33|ETH0_TXRX3_M|LAN.TXRXM_D|11| -|D||||-|J1.35|DGND|DGND| -| -|G||||-| rowspan="4" |J1.37| rowspan="4" |GPIO1_IO00| rowspan="4" |CPU.GPIO1_IO00| rowspan="4" |T6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO00|-|ALT1|CCM_ENET_PHY_REF_CLK_ROOT|-|ALT5|ANAMIX_REF_CLK_32K|-|ALT6|CCM_EXT_CLK1|-| rowspan="4" |J1.39| rowspan="4" |GPIO1_IO01| rowspan="4" |CPU.GPIO1_IO01| rowspan="4" |T7| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" |Internally used for ETH PHY reset, do not connect|ALT0|GPIO1_IO01|-|ALT1|PWM1_OUT|-|ALT5|ANAMIX_REF_CLK_25M|-|ALT6|CCM_EXT_CLK2|-| rowspan="3" |J1.41| rowspan="3" |SPDIF_EXT_CLK| rowspan="3" |CPU.SPDIF_EXT_CLK| rowspan="3" |E6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SPDIF1_EXT_CLK|-|ALT1|PWM1_OUT|-|ALT5|GPIO5_IO05|-| rowspan="3" |J1.43| rowspan="3" |GPIO1_IO13| rowspan="3" |CPU.GPIO1_IO13| rowspan="3" |K6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |Internally used, do not connect|ALT0|GPIO1_IO13|-|ALT1|USB1_OTG_OC|-|ALT5|PWM2_OUT|-|J1.45|VDD_PHY_1V8||||||||-| rowspan="3" |J1.47| rowspan="3" |ECSPI2_SCLK| rowspan="3" |CPU.ECSPI2_SCLK| rowspan="3" |C5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_SCLK|-|ALT1|UART4_RX|-|ALT5|GPIO5_IO10|-| rowspan="3" |J1.49| rowspan="3" |ECSPI2_MOSI| rowspan="3" |CPU.ECSPI2_MOSI| rowspan="3" |E5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_MOSI|-|ALT1|UART4_TX|-|ALT5|GPIO5_IO11|-| rowspan="3" |J1.51| rowspan="3" |GPIO1_IO08| rowspan="3" |CPU.GPIO1_IO08| rowspan="3" |N7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO08|-|ALT1|ENET1_1588_EVENT0_IN|-|ALT5|USDHC2_RESET_B|-| rowspan="3" |J1.53| rowspan="3" |GPIO1_IO09| rowspan="3" |CPU.GPIO1_IO09| rowspan="3" |M7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO09|-|ALT1|ENET1_1588_EVENT0_OUT|-|ALT5|SDMA2_EXT_EVENT0|-| rowspan="3" |J1.55| rowspan="3" |ECSPI2_MISO| rowspan="3" |CPU.ECSPI2_MISO| rowspan="3" |B5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_MISO|-|ALT1|UART4_CTS_B|-|ALT5|GPIO5_IO12|-|J1.57|DGND |DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="3" |J1.59| rowspan="3" |ECSPI2_SS0| rowspan="3" |CPU.ECSPI2_SS0| rowspan="3" |A5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI2_SS0|-|ALT1|UART4_RTS_B|-|ALT5|GPIO5_IO13|-| rowspan="3" |J1.61| rowspan="3" |GPIO1_IO05| rowspan="3" |CPU.GPIO1_IO05| rowspan="3" |P7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connect|ALT0|GPIO1_IO05|-|ALT1|M4_NMI|-|ALT5|CCM_PMIC_READY|-| rowspan="3" |J1.63| rowspan="3" |I2C2_SCL| rowspan="3" |CPU.I2C2_SCL| rowspan="3" |G7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|I2C2_SCL|-|ALT1|ENET1_1588_EVENT1_IN|-|ALT5|GPIO5_IO16|-| rowspan="3" |J1.65| rowspan="3" |I2C2_SDA| rowspan="3" |CPU.I2C2_SDA| rowspan="3" |F7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|I2C2_SDA|-|ALT1|ENET1_1588_EVENT1_OUT|-|ALT5|GPIO5_IO17|-| rowspan="4" |J1.67| rowspan="4" |GPIO1_IO06| rowspan="4" |CPU.GPIO1_IO06| rowspan="4" |N5| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect|ALT0|GPIO1_IO06|-|ALT1|ENET1_MDC|-|ALT5|USDHC1_CD_B|-|ALT6|CCM_EXT_CLK3|-| rowspan="3" |J1.69| rowspan="3" |SAI2_RXC| rowspan="3" |CPU.SAI2_RXC| rowspan="3" |H3| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_RX_BCLK|-|ALT1|SAI5_TX_BCLK|-|ALT5|GPIO4_IO22|-| rowspan="3" |J1.71| rowspan="3" |SAI2_RXFS| rowspan="3" |CPU.SAI2_RXFS| rowspan="3" |J4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|SAI2_RX_SYNC|-|ALT1|SAI5_TX_SYNC|-|ALT5|GPIO4_IO21|-|J1.73|DGND |DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="2" |J1.75| rowspan="2" |SD2_DATA0| rowspan="2" |CPU.SD2_DATA0| rowspan="2" |N22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_DATA0|-|ALT5|GPIO2_IO15|-| rowspan="2" |J1.77| rowspan="2" |SD2_DATA1| rowspan="2" |CPU.SD2_DATA1| rowspan="2" |N21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_DATA1|-|ALT5|GPIO2_IO16|-| rowspan="2" |J1.79| rowspan="2" |SD2_DATA2| rowspan="2" |CPU.SD2_DATA2| rowspan="2" |P22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_DATA2|-|ALT5|GPIO2_IO17|-| rowspan="2" |J1.81| rowspan="2" |SD2_DATA3| rowspan="2" |CPU.SD2_DATA03| rowspan="2" |P21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_DATA3|-|ALT5|GPIO2_IO18|-| rowspan="2" |J1.83| rowspan="2" |SD2_CMD| rowspan="2" |CPU.SD2_CMD| rowspan="2" |M22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CMD|-|ALT5|GPIO2_IO14|-| rowspan="2" |J1.85| rowspan="2" |SD2_CLK| rowspan="2" |CPU.SD2_CLK| rowspan="2" |L22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CLK|-|ALT5|GPIO2_IO13|-|J1.87|DGND |DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="3" |J1.89| rowspan="3" |UART3_TXD| rowspan="3" |CPU.UART3_TXD| rowspan="3" |B7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART3_TX|-|ALT1|UART1_RTS_B|-|ALT5|GPIO5_IO27|-| rowspan="3" |J1.91| rowspan="3" |UART3_RXD| rowspan="3" |CPU.UART3_RXD| rowspan="3" |A6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART3_RX|-|ALT1|UART1_CTS_B|-|ALT5|GPIO5_IO26|-| rowspan="4" |J1.93| rowspan="4" |UART4_TXD| rowspan="4" |CPU.UART4_TXD| rowspan="4" |D7| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|UART4_TX|-|ALT1|UART2_RTS_B|-|ALT2|PCIE2_CLKREQ_B|-|ALT5|GPIO5_IO29|-| rowspan="4" |J1.95| rowspan="4" |UART4_RXD| rowspan="4" |CPU.UART4_RXD| rowspan="4" |C6| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|UART4_RX|-|ALT1|UART2_CTS_B|-|ALT2|PCIE1_CLKREQ_B|-|ALT5|GPIO5_IO28|-| rowspan="2" |J1.97| rowspan="2" |SD2_WP| rowspan="2" |CPU.SD2_WP| rowspan="2" |M21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_WP|-|ALT5|GPIO2_IO20|-| rowspan="2" |J1.99| rowspan="2" |SD2_RST_B| rowspan="2" |CPU.SD2_RESET_B| rowspan="2" |R22| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_RESET_B|-|ALT5|GPIO2_IO19|-|J1.101|HDMI_DDC_SCL|CPU.HDMI_DDC_SCL|R3|VDD_PHY_1V8|I/O||||-|J1.103|HDMI_DDC_SDA|CPU.HDMI_DDC_SDA|P3|VDD_PHY_1V8|I/O||||-|J1.105|HDMI_AUX_N|CPU.HDMI_AUX_N|V2| -|D|connected with capacitor in series|||-|J1.107|HDMI_AUX_P|CPU.HDMI_AUX_P|V1| -|D|connected with capacitor in series|||-|J1.109|DGND |DGND| -|<nowiki>-</nowiki>|G||||-|J1.111|HDMI_TX_M_LN_3|CPU.HDMI_TX_M_LN_3|M2| -|D|connected with capacitor in series|||-|J1.113|HDMI_TX_P_LN_3|CPU.HDMI_TX_P_LN_3|M1| -|D|connected with capacitor in series|||-|J1.115|HDMI_TX_M_LN_0|CPU.HDMI_TX_M_LN_0|T2| -|D|connected with capacitor in series|||-|J1.117|HDMI_TX_P_LN_0|CPU.HDMI_TX_P_LN_0|T1| -|D|connected with capacitor in series|||-|J1.119|HDMI_TX_M_LN_1|CPU.HDMI_TX_M_LN_1|U1| -|D|connected with capacitor in series|||-|J1.121|HDMI_TX_P_LN_1|CPU.HDMI_TX_P_LN_1|U2| -|D|connected with capacitor in series|||-|J1.123|HDMI_TX_M_LN_2|CPU.HDMI_TX_M_LN_2|N1| -|D|connected with capacitor in series|||-|J1.125|HDMI_TX_P_LN_2|CPU.HDMI_TX_P_LN_2|N2| -|D|connected with capacitor in series|||-|J1.127|HDMI_CEC|CPU.HDMI_CEC|W3|VDD_PHY_1V8|I/O||||-|J1.129|HDMI_HPD|CPU.HDMI_HPD|W2|VDD_PHY_1V8|I/O||||-|J1.131|DGND |DGND| -|<nowiki>-</nowiki>|G||||-|J1.133|LVDS0_CLK_N|BRIDGE.A_CLKN|F9| -|D||||-|J1.135|LVDS0_CLK_P|BRIDGE.A_CLKP|F8| -|D||||-|J1.137|LVDS0_TX0_N|BRIDGE.A_Y0N|C9| -|D||||-|J1.139|LVDS0_TX0_P|BRIDGE.A_Y0P|C8| -|D||||-|J1.141|LVDS0_TX1_N|BRIDGE.A_Y1N|D9| -|D||||-|J1.143|LVDS0_TX1_P|BRIDGE.A_Y1P|D8| -|D||||-|J1.145|LVDS0_TX2_N|BRIDGE.A_Y2N|E9| -|D||||-|J1.147|LVDS0_TX2_P|BRIDGE.A_Y2P|E8| -|D||||-|J1.149|LVDS0_TX3_N|BRIDGE.A_Y3N|G9| -|D||||-|J1.151|LVDS0_TX3_P|BRIDGE.A_Y3P|G8| -|D||||-|J1.153|DGND |DGND| -|<nowiki>-</nowiki>|G||||-|J1.155|LVDS1_CLK_N|BRIDGE.B_CLKN|A6| -|D||||-|J1.157|LVDS1_CLK_P|BRIDGE.B_CLKP|B6| -|D||||-|J1.159|LVDS1_TX0_N|BRIDGE.B_Y0N|A3| -|D||||-|J1.161|LVDS1_TX0_P|BRIDGE.B_Y0P|B3| -|D||||-|J1.163|LVDS1_TX1_N|BRIDGE.B_Y1N|A4| -|D||||-|J1.165|LVDS1_TX1_P|BRIDGE.B_Y1P|B4| -|D||||-|J1.167|LVDS1_TX2_N|BRIDGE.B_Y2N|A5| -|D||||-|J1.169|LVDS1_TX2_P|BRIDGE.B_Y2P|B5| -|D||||-|J1.171|LVDS1_TX3_N|BRIDGE.B_Y3N|A7| -|D||||-|J1.173|LVDS1_TX3_P|BRIDGE.B_Y3P|B7| -|D||||-|J1.175|DGND |DGND| -|<nowiki>-</nowiki>|G||||-| rowspan="2" |J1.177| rowspan="2" |SD2_CD_B| rowspan="2" |CPU.SD2_CD_B| rowspan="2" |L21| rowspan="2" |NVCC_3V3| rowspan="2" |I/O| rowspan="2" ||ALT0|USDHC2_CD_B|-|ALT5|GPIO2_IO12|-| rowspan="3" |J1.179| rowspan="3" |ECSPI1_SS0| rowspan="3" |CPU.ECSPI1_SS0| rowspan="3" |D4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SS0|-|ALT1|UART3_RTS_B|-|ALT5|GPIO5_IO09|-| rowspan="3" |J1.181| rowspan="3" |ECSPI1_SCLK| rowspan="3" |CPU.ECSPI1_SCLK| rowspan="3" |D5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_SCLK|-|ALT1|UART3_RX|-|ALT5|GPIO5_IO06|-| rowspan="3" |J1.183| rowspan="3" |ECSPI1_MISO| rowspan="3" |CPU.ECSPI1_MISO| rowspan="3" |B4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_MISO|-|ALT1|UART3_CTS_B|-|ALT5|GPIO5_IO08|-| rowspan="3" |J1.185| rowspan="3" |GPIO1_IO03| rowspan="3" |CPU.GPIO1_IO03| rowspan="3" |P4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO03|-|ALT1|USDHC1_VSELECT|-|ALT5|SDMA1_EXT_EVENT0|-| rowspan="3" |J1.187| rowspan="3" |UART2_TXD| rowspan="3" |CPU.UART2_TXD| rowspan="3" |D6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |used as default Linux console|ALT0|UART2_TX|-|ALT1|ECSPI3_SS0|-|ALT5|GPIO5_IO25|-| rowspan="3" |J1.189| rowspan="3" |UART2_RXD| rowspan="3" |CPU.UART2_RXD| rowspan="3" |B6| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" |used as default Linux console|ALT0|UART2_RXD|-|ALT1|ECSPI3_MISO|-|ALT5|GPIO5_IO24|-| rowspan="3" |J1.191| rowspan="3" |UART1_TXD| rowspan="3" |CPU.UART1_TXD| rowspan="3" |A7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART1_TX|-|ALT1|ECSPI3_MOSI|-|ALT5|GPIO5_IO23|-| rowspan="3" |J1.193| rowspan="3" |UART1_RXD| rowspan="3" |CPU.UART1_RXD| rowspan="3" |C7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|UART1_RXD|-|ALT1|ECSPI3_SCLK|-|ALT5|GPIO5_IO22|-| rowspan="3" |J1.195| rowspan="3" |ECSPI1_MOSI| rowspan="3" |CPU.ECSPI1_MOSI| rowspan="3" |A4| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|ECSPI1_MOSI|-|ALT1|UART3_TX|-|ALT5|GPIO5_IO07|-| rowspan="4" |J1.197| rowspan="4" |GPIO1_IO14| rowspan="4" |CPU.GPIO1_IO14| rowspan="4" |K7| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|GPIO1_IO14|-|ALT1|USB2_OTG_PWR|-|ALT5|PWM3_OUT|-|ALT6|CCM_CLKO1|-| rowspan="3" |J1.199| rowspan="3" |GPIO1_IO04| rowspan="3" |CPU.GPIO1_IO04| rowspan="3" |P5| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO04|-|ALT1|USDHC2_VSELECT|-|ALT5|SDMA1_EXT_EVENT1|-| rowspan="3" |J1.201| rowspan="3" |GPIO1_IO12| rowspan="3" |CPU.GPIO1_IO12| rowspan="3" |L7| rowspan="3" |NVCC_3V3| rowspan="3" |I/O| rowspan="3" ||ALT0|GPIO1_IO12|-|ALT1|USB1_OTG_PWR|-|ALT5|SDMA2_EXT_EVENT1|-|J1.203|DGND |DGND| -|<nowiki>-</nowiki>|G|A|A|A
|-
|}
===Pinout Table EVEN pins declaration ===
{| class="wikitable"
| rowspan="4" |CPU.SAI5_MCLK
| rowspan="4" |K4
| rowspan="4" |NVCC_3V3| rowspan="4" |I/O
| rowspan="4" |
|ALT0
|SAI5_MCLK
|-
|
|
|ALT1
|SAI1_TX_BCLK
|-
|
|
|ALT2
|SAI4_MCLK
|-
|
|
|ALT5
|GPIO3_IO25
U0009
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