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Created page with "<section begin=History/> {| style="border-collapse:collapse; " !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History |- !style="border-le..."
<section begin=History/>
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|1.0.0
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Sep 2020
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New layout documentation
|-
|}
<section end=History/>
<section begin=Body/>
== Processor and memory subsystem ==
The heart of AXEL Lite module is composed by the following components:
* i.MX6 SoC application processor
* Power supply unit
* DDR memory banks
* NOR and NAND flash banks
* SO-DIM 204 pin connector with interfaces signals
This chapter shortly describes the main Axel Lite components.
=== Processor Info ===
{| class="wikitable" |
| align="center" style="background:#f0f0f0;"|'''Processor'''
| align="center" style="background:#f0f0f0;"|'''# Cores'''
| align="center" style="background:#f0f0f0;"|'''Clock'''
| align="center" style="background:#f0f0f0;"|'''L2 Cache'''
| align="center" style="background:#f0f0f0;"|'''DDR3'''
| align="center" style="background:#f0f0f0;"|'''Graphics Acceleration'''
| align="center" style="background:#f0f0f0;"|'''IPU'''
| align="center" style="background:#f0f0f0;"|'''VPU'''
| align="center" style="background:#f0f0f0;"|'''SATA-II'''
|-
| i.MX6 Solo || 1 ||800 MHz<br>1 GHz ||512 KB ||32 bit @ 400 MHz ||3D: Vivante GC880<br>2D: Vivante GC320<br>Vector: N.A. ||1x ||1x ||N.A.
|-
| i.MX6 Dual || 2 ||850 MHz<br>1 GHz<br>1.2 GHz ||1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
|-
| i.MX6 Quad || 4 ||850 MHz<br>1 GHz<br>1.2 GHz ||1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
|-
|+ align="bottom" style="caption-side: bottom" | Table: i.MX6 models comparison
|}
=== RAM memory bank ===
DDR3 SDRAM memory bank is composed by 4x 16-bit width chips resulting in a 64-bit combined width bank. The following table reports the SDRAM specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
|-
| '''Size min'''||512 MB
|-
| '''Size max'''||4 GB
|-
| '''Width'''||64 bit
|-
| '''Speed'''||533 MHz
|-
|}
=== NOR flash bank ===
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI channel 5 and by default it acts as boot memory. The following table reports the NOR flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||eCSPI channel 5
|-
| '''Size min'''||8 MB
|-
| '''Size max'''||64 MB
|-
| '''Chip select'''||ECSPI5_SS0
|-
| '''Bootable'''||Yes
|-
|}
=== NAND flash bank ===
On board main storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Raw NAND flash controller
|-
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyte
|-
| '''Size min'''||128 MB
|-
| '''Size max'''||2 GB
|-
| '''Width'''||8 bit
|-
| '''Chip select'''||NANDF_CS0
|-
| '''Bootable'''||Yes
|-
|}
=== Memory map ===
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX Applications Processor Reference Manual.
=== Power supply unit ===
AXEL Lite embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
----
[[Category:AXEL Lite]]
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|1.0.0
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Sep 2020
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New layout documentation
|-
|}
<section end=History/>
<section begin=Body/>
== Processor and memory subsystem ==
The heart of AXEL Lite module is composed by the following components:
* i.MX6 SoC application processor
* Power supply unit
* DDR memory banks
* NOR and NAND flash banks
* SO-DIM 204 pin connector with interfaces signals
This chapter shortly describes the main Axel Lite components.
=== Processor Info ===
{| class="wikitable" |
| align="center" style="background:#f0f0f0;"|'''Processor'''
| align="center" style="background:#f0f0f0;"|'''# Cores'''
| align="center" style="background:#f0f0f0;"|'''Clock'''
| align="center" style="background:#f0f0f0;"|'''L2 Cache'''
| align="center" style="background:#f0f0f0;"|'''DDR3'''
| align="center" style="background:#f0f0f0;"|'''Graphics Acceleration'''
| align="center" style="background:#f0f0f0;"|'''IPU'''
| align="center" style="background:#f0f0f0;"|'''VPU'''
| align="center" style="background:#f0f0f0;"|'''SATA-II'''
|-
| i.MX6 Solo || 1 ||800 MHz<br>1 GHz ||512 KB ||32 bit @ 400 MHz ||3D: Vivante GC880<br>2D: Vivante GC320<br>Vector: N.A. ||1x ||1x ||N.A.
|-
| i.MX6 Dual || 2 ||850 MHz<br>1 GHz<br>1.2 GHz ||1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
|-
| i.MX6 Quad || 4 ||850 MHz<br>1 GHz<br>1.2 GHz ||1 MB ||64 bit @ 533 MHz ||3D: Vivante GC2000<br>2D: Vivante GC320<br>Vector: Vivante GC335 ||2x ||2x || Yes
|-
|+ align="bottom" style="caption-side: bottom" | Table: i.MX6 models comparison
|}
=== RAM memory bank ===
DDR3 SDRAM memory bank is composed by 4x 16-bit width chips resulting in a 64-bit combined width bank. The following table reports the SDRAM specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Multi-mode DDR controller (MMDC)
|-
| '''Size min'''||512 MB
|-
| '''Size max'''||4 GB
|-
| '''Width'''||64 bit
|-
| '''Speed'''||533 MHz
|-
|}
=== NOR flash bank ===
NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI channel 5 and by default it acts as boot memory. The following table reports the NOR flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||eCSPI channel 5
|-
| '''Size min'''||8 MB
|-
| '''Size max'''||64 MB
|-
| '''Chip select'''||ECSPI5_SS0
|-
| '''Bootable'''||Yes
|-
|}
=== NAND flash bank ===
On board main storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Raw NAND flash controller
|-
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyte
|-
| '''Size min'''||128 MB
|-
| '''Size max'''||2 GB
|-
| '''Width'''||8 bit
|-
| '''Chip select'''||NANDF_CS0
|-
| '''Bootable'''||Yes
|-
|}
=== Memory map ===
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX Applications Processor Reference Manual.
=== Power supply unit ===
AXEL Lite embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
----
[[Category:AXEL Lite]]
