LCD interface (AXEL ULite)
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Introduction[edit | edit source]
i.MX6UL processor on AXEL ULite system-on-module (SOM for short) has a general purpose display controller to drive a wide range of display devices with different resolution and bpp (bit-per-pixel) configuration.
Please refer to i.MX 6UltraLite Applications Processor Reference Manual chapter eLCDIF Pin Usage by Interface Mode for more information on LCD interface usage
Pin mapping[edit | edit source]
LCD signals configurations for the most used 18 and 24 bpp are detailed in the following table.
| Signal name | 18 bpp | 24 bpp | SOM pin number |
|---|---|---|---|
| LCD_ENABLE | DE | DE | 124 |
| LCD_VSYNC | VSYNC | VSYNC | 128 |
| LCD_HSYNC | HSYNC | HSYNC | 130 |
| LCD_CLK | CLK | CLK | 132 |
| LCD_D00 | B0 | B0 | 134 |
| LCD_D01 | B1 | B1 | 136 |
| LCD_D02 | B2 | B2 | 138 |
| LCD_D03 | B3 | B3 | 140 |
| LCD_D04 | B4 | B4 | 142 |
| LCD_D05 | B5 | B5 | 144 |
| LCD_D06 | G0 | B6 | 148 |
| LCD_D07 | G1 | B7 | 150 |
| LCD_D08 | G2 | G0 | 152 |
| LCD_D09 | G3 | G1 | 154 |
| LCD_D10 | G4 | G2 | 156 |
| LCD_D11 | G5 | G3 | 158 |
| LCD_D12 | R0 | G4 | 160 |
| LCD_D13 | R1 | G5 | 162 |
| LCD_D14 | R2 | G6 | 166 |
| LCD_D15 | R3 | G7 | 168 |
| LCD_D16 | R4 | R0 | 170 |
| LCD_D17 | R5 | R1 | 172 |
| LCD_D18 | x | R2 | 174 |
| LCD_D19 | x | R3 | 176 |
| LCD_D20 | x | R4 | 178 |
| LCD_D21 | x | R5 | 180 |
| LCD_D22 | x | R6 | 182 |
| LCD_D23 | x | R7 | 184 |
The DOTCLK interface is popularly called the RGB interface if the ENABLE signal is present. The RGB interface has programmable timing and parameters for supporting a wide variety of displays.
