Reset scheme (AxelUltra)
Revision as of 13:52, 25 March 2014 by DevWikiAdmin (talk | contribs) (Created page with "{{InfoBoxTop}} {{AppliesToAxel}} {{InfoBoxBottom}} == Reset scheme and control signals == The following picture shows the simplified block diagram of reset scheme and voltag...")
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Reset scheme and control signals[edit | edit source]
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
The available reset signals are described in detail in the following sections.
CPU_PORn[edit | edit source]
Three different sources can assert this active-low signal:
- PMIC
- multiple-voltage monitor: this device monitors several critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
- watchdog timer: even if MX6 processor integrates a watchdog timer (WDT), an external WDT (Maxim MAX6373KA+) is avalible to maximize reliability
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state after reset occurrence.
