Reset scheme (AxelUltra)
Reset scheme and control signals
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:
- voltage applied to PMICS's VIN pin
- in case of AxelUltra this pin is connected to 2V8-4V5 power rail
- voltage applied to PMICS's LICELL pin
- in case of AxelUltra this pin is connected to J1.126 pin (PMIC_LICELL)
- PMIC's VSNVSCTL register configuration.
Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.
For more details please refer to section VSNVS LDO/Switch of MMPF0100 Advance Information document.
Three different sources can assert this active-low signal:
- multiple-voltage monitor: this device monitors several critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
- MRSTn: this signal is connected to the RESET IN input of the voltage monitor. MRSTn is pulled-up to processor's I/O voltage with 2.2 kOhm resistor.
- watchdog timer: even if MX6 processor integrates a watchdog timer (WDT), an external WDT (Maxim MAX6373KA+) is avalible to maximize reliability
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state after reset occurrence.
Handling CPU-initiated software reset
By default, MX6 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly. For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
This technique is implemented in XELK. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to U22 chip of AxelEVB-Lite carrier board), driving PMIC_PWRON.