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*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4/settings32.sh</code>}}{{efn|Passing the -tclargs "-bitstream" parameters allows for automatic building of the FPGA bitstream.}}:
<pre>
. /opt/Xilinx/Vivado/2014.4/settings64.sh1sh
vivado -mode tcl -source build_project.tcl -notrace -tclargs "-bitstream"
</pre>
*once the Xilinx SDK is ready, perform the following operations from the GUI:
**Click on ''File -> New -> Application Project''
**Select the Project Name: ''<code>bora_FSBL''</code>
**Click ''Next''
**Select ''Template: Zynq FSBL''
**Check that the patch is correctly applied to the source code and click on ''Finish''
**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):
***Apply <code><bora_repo>/patch/AR65145_ps7_init_c.patch</code> on <code>ps7_init.c</code> under <code>''bora_wrapper_hw_platform_0</code>''***Apply <code><bora_repo>/patch/AR65145_ps7_init_tcl.patch</code> on <code>ps7_init.tcl</code> under <code>''bora_wrapper_hw_platform_0</code>''
*the FSBL (ELF file) is built automatically
*create the binary from the FSBL ELF chosing one of the following options:
*launch the Vivado Design Suite GUI with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4/settings32.sh</code>}}:
<pre>
. /opt/Xilinx/Vivado/2014.4/settings64.sh1sh
vivado
</pre>
**Click on ''File -> New -> Application Project''
**Select the Project Name: <code>bora_FSBL</code>
**Click ''Next''**Select ''Template: Zynq FSBL''**Click on ''Finish''
**Apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..
*From ''Browse... '' open the file <code><bora_repo>/patch/<belk/belkx>-sd-boot.patch</code>**Click ''Next''
**Select ''Apply the patch to the selected file, folder or project'': and select <code>main.c</code> from ''bora_FSBL -> src''
**Click ''Next''
**Check that the patch is correctly applied to the source code and click on ''Finish''
**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):
***Apply <code><bora_repo>/patch/AR65145_ps7_init_c.patch</code> on <code>ps7_init.c</code> under <code>''bora_wrapper_hw_platform_0</code>''***Apply <code><bora_repo>/patch/AR65145_ps7_init_tcl.patch</code> on <code>ps7_init.tcl</code> under <code>''bora_wrapper_hw_platform_0</code>''
*the FSBL (ELF file) is built automatically
*create the binary from the FSBL ELF chosing one of the following options:
