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*assuming that a local repository has not been created, clone the remote BORA git repository:
*:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
*copy the <code><bora_repo>/boards/board_parts/zynq/BELK_2.2.0BORA</code> directory and <code><bora_repo>/boards/board_parts/zynq/BORAX</code> directories to <code><vivado_2014.4_install_dir>/data/boards/board_parts/zynq/</code> :
<pre>
cd <bora_repo>
sudo cp -r boards/board_parts/zynq/BELK_2BORA /opt/Xilinx/Vivado/2014.2.0 4/data/boards/board_parts/zynq/sudo cp -r boards/board_parts/zynq/BORAX /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/
</pre>
*enter the git directory and launch the following commandto set the project directory
*:<code>export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk</code>
*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4/settings32.sh</code>}}{{efn|Passing the -tclargs "-bitstream" parameters allows for automatic building of the FPGA bitstream.}}:
vivado -mode tcl -source build_project.tcl -notrace -tclargs "-bitstream"
</pre>
*the <code>build_project</code> script allows user to select BORA or BORAX target
*at the end of the bitstream build process, the <code>build_project</code> script allows to automatically export hardware and lauch SDK to build the FSBL
*once the Xilinx SDK is ready, perform the following operations from the GUI:
**Click ''Next''
**Check that the patch is correctly applied to the source code and click on ''Finish''
**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):
***Apply <code><bora_repo>/patch/AR65145_ps7_init_c.patch</code> on <code>ps7_init.c</code> under <code>bora_wrapper_hw_platform_0</code>
***Apply <code><bora_repo>/patch/AR65145_ps7_init_tcl.patch</code> on <code>ps7_init.tcl</code> under <code>bora_wrapper_hw_platform_0</code>
*the FSBL (ELF file) is built automatically
*create the binary from the FSBL ELF chosing one of the following options:
*start the Zynq development server and login into the system
*assuming that a local repository has not been created, clone the remote BORA git repository:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
*copy the <code><bora_repo>/boards/board_parts/zynq/BELK_2.2.0BORA</code> directory and <code><bora_repo>/boards/board_parts/zynq/BORAX</code> directories to <code><vivado_2014.4_install_dir>/data/boards/board_parts/zynq/</code> :
<pre>
cd <bora_repo>
sudo cp -r boards/board_parts/zynq/BELK_2BORA /opt/Xilinx/Vivado/2014.2.0 4/data/boards/board_parts/zynq/sudo cp -r boards/board_parts/zynq/BORAX /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/
</pre>
*launch the Vivado v2014Design Suite GUI with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4/settings32.sh</code>}}:<pre>. /opt/Xilinx/Vivado/2014.4 and /settings64.sh1vivado</pre>*from the start page click on ''Create New Project''
*click ''Next''
*select the directory build project, insert the name of the project ''Project Name'' and click ''Next''
*select ''RTL Project'', enable ''Do not specify sources at this time'' and click ''Next''
*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''BELK 2.2.0BORA'' or ''BORAX'' depending on target SOM and click ''Next''
*check the summary page and click ''Finish''
*in the Vivado GUI click on ''Create Block Design'' from the ''Flow Navigator''
*this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation'' from the upper suggestions bar
*check that ''Apply Board Preset'' is selected and click ''OK''
*this applies the default settings for BORA /BORAX and creates the I/O ports for the DDR and MIO pins and for the UART_0 and CAN_0 interfaces
*manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design
*from the sources tab, select the BORA /BORAX block design (<code>bora.bd</code>) as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''
*on the next window, select ''Copy generated wrapper'' to allow user edits and click ''OK''
*this creates the Verilog <code>bora_wrapper.v</code> file. If this file is not automatically included in the project, add it using the ''Add sources'' option
**Click on Finish
**Apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..
*From Browse... open the file <code><bora_repo>/patch/<belk/belkx>-sd-boot.patch</code>
**Click Next
**Select ''Apply the patch to the selected file, folder or project'': and select <code>main.c</code> from ''bora_FSBL -> src''
**Click ''Next''
**Check that the patch is correctly applied to the source code and click on ''Finish''
**With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):
***Apply <code><bora_repo>/patch/AR65145_ps7_init_c.patch</code> on <code>ps7_init.c</code> under <code>bora_wrapper_hw_platform_0</code>
***Apply <code><bora_repo>/patch/AR65145_ps7_init_tcl.patch</code> on <code>ps7_init.tcl</code> under <code>bora_wrapper_hw_platform_0</code>
*the FSBL (ELF file) is built automatically
*create the binary from the FSBL ELF chosing one of the following options:
