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Processor and memory subsystem (Bora)

627 bytes added, 13:55, 3 November 2021
Processor Info
|+ align="bottom" style="caption-side: bottom" | Table: XC7-Z0x0 comparison
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On PS side, the following peripherals and devices are connected to MIO signals:
* Serial NOR fl ash (MIO [6:1])
* NAND fl ash (MIO [0], [14:2])
* UART1 (MIO [49:48])
* I2C temperature sensor (MIO [47:46])
* I2C MEMS RTC (MIO [47:46])
* Gigabit Ethernet PHY (MIO [27:16])
* USBOTG PHY (MIO [39:28])
* SD/MMC (MIO [45:40])
 
Since these devices are considered essential, they have been connected to MIO signals in order to make them always functional, even if PL is not programmed.
These peripherals represent the default configuration for the BORA SOM, but other configurations can be implemented changing the pin multiplexing
=== RAM memory bank ===
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