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→Integrated FPGA
analog to digital converter (XADC), clock management tiles (CMT), a configuration block with 256b AES for decryption and SHA for authentication, configurable I/Os (with differential signaling capabilities).
BORA customers are able to differentiate their product in hardware by customizing their applications using PL.
PL subsystem provides a lot of configurable I/Os, grouped in banks denoted as Bank x (eg Bank 9, Bank 13 etc.). Two types of such banks exist: HR 1 and HP 2.
Some of the MIO signals can be routed outside the component via PL subsystem. This technique is called EMIO routing.
=== Power supply unit ===