3,260
edits
Changes
→J2 odd pins (1 to 139)
==J2 odd pins (1 to 139)==
{| class="wikitable" {{table}}
| align="center" style="background:#f0f0f0;"|'''Pin'''
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
| align="center" style="background:#f0f0f0;"|'''Supply Group'''
| align="center" style="background:#f0f0f0;"|'''Type'''
| align="center" style="background:#f0f0f0;"|'''Voltage'''
| align="center" style="background:#f0f0f0;"|'''Note'''
|-
| J2.2||DGND||DGND||-||||G||||
|-
| J2.4||GPMC_D1||CPU.GPMC_D[1]/BTMODE[1]||Y28||||I/O||||
|-
| J2.6||GPMC_D3||CPU.GPMC_D[3]/BTMODE[3]||W27||||I/O||||
|-
| J2.8||GPMC_D5||CPU.GPMC_D[5]/BTMODE[5]||AA28||||I/O||||
|-
| J2.10||GPMC_D7||CPU.GPMC_D[7]/BTMODE[7]||V25||||I/O||||
|-
| J2.12||SATA_TXP||CPU.SATA_TXP0||AB2||||O||||
|-
| J2.14||SATA_TXN||CPU.SATA_TXN0||AB1||||O||||
|-
| J2.16||SATA_RXP||CPU.SATA_RXP0||AA1||||I||||
|-
| J2.18||SATA_RXN||CPU.SATA_RXN0||AA2||||I||||
|-
| J2.20||DGND||DGND||-||||G||||
|-
| J2.22||GPMC_A1/SD2_DAT3||CPU.SD2_DAT[3]/GPMC_A[1]/GP2[5]||J28||||I/O||||
|-
| J2.24||GPMC_A3/SD2_DAT1||CPU.SD2_DAT[1]_SDIRQn/GPMC_A[3]/GP1[13]||M24||||I/O||||
|-
| J2.26||GPMC_A5/CAM_D3||CPU.VOUT[1]_G_Y_YC[1]/CAM_D[3]/GPMC_A[5]/UART4_RXD/GP0[22]||AD18||||I/O||||
|-
| J2.28||GPMC_A7/CAM_D1||CPU.VOUT[1]_R_CR[1]/CAM_D[1]/GPMC_A[7]/UART4_CTSn/GP0[24]||AC19||||I/O||||
|-
| J2.30||GPMC_A9/CAM_HS||CPU.VOUT[1]_B_CB_C[1]/CAM_HS/GPMC_A[9]/UART2_RXD/GP0[26]||AE23||||I/O||||
|-
| J2.32||GPMC_A11/CAM_FLD/CAM_WEn||CPU.VOUT[1]_FLD/CAM_FLD/CAM_WEn/GPMC_A[11]/UART2_CTSn/GP0[28]||AB23||||I/O||||
|-
| J2.34||GPMC_A13/I2C2_SCL||CPU.VOUT[1]_G_Y_YC[2]/GPMC_A[13]/VIN[1]A_D[21]/HDMI_SCL/SPI[2]_SCS[2]n/I2C[2]_SCL/GP3[20]||AF27||||I/O||||
|-
| J2.36||GPMC_A15||CPU.VOUT[1]_R_CR[2]/GPMC_A[15]/VIN[1]A_D[23]/HDMI_HPDET/SPI[2]_D[1]/GP3[22]||AE27||||I/O||||
|-
| J2.38||GPMC_A17||CPU.GPMC_A[17]/GP2[6]||V23||||I/O||||
|-
| J2.40||GPMC_A19||CPU.GPMC_A[19]/TIM3_IO/GP1[14]||AC27||||I/O||||
|-
| J2.42||GPMC_A21||CPU.GPMC_A[21]/SPI[2]_D[0]/GP1[16]||AC28||||I/O||||
|-
| J2.44||GPMC_A23||CPU.GPMC_A[23]/SPI[2]_SCLK/HDMI_HPDET/TIM5_IO/GP1[18]||AA26||||I/O||||
|-
| J2.46||VOUT1_G_Y_YC5/GP3_9||CPU.VOUT[1]_G_Y_YC[5]/EMAC[1]_MRXDV/VIN[1]A_D[10]/PATA_D[2]/GP3[9]||AG26||||I/O||||
|-
| J2.48||GPMC_CS1n||CPU.GPMC_CS[1]n/GPMC_A[25]/GP1[24]||K28||||I/O||||
|-
| J2.50||GPMC_CS3n||CPU.GPMC_CS[3]n/VIN[1]B_CLK/SPI[2]_SCS[0]n/GP1[26]||P26||||I/O||||
|-
| J2.52||VOUT1_G_Y_YC7/GP3_11||CPU.VOUT[1]_G_Y_YC[7]/EMAC[1]_MTXD[0]/VIN[1]A_D[12]/PATA_D[4]/GP3[11]||AF26||||I/O||||
|-
| J2.54||DGND||DGND||-||||G||||
|-
| J2.56||GPMC_OEn_REn||GPMC_OEn_REn||T27||||O||||
|-
| J2.58||GPMC_BE0n_CLE/GPMC_A25/EDMA_EVT2/TIM6_IO/GP1_29||CPU.GPMC_BE[0]n_CLE/GPMC_A[25]/EDMA_EVT2/TIM6_IO/GP1[29]||U27||||I/O||||
|-
| J2.60||VIN[0]B_CLK/GP1[9]||CPU.VIN[0]B_CLK/CLKOUT0/GP1[9]||AE17||||I/O||||(1)
|-
| ||VRTC||MTR||-||||O||||(1)
|-
| J2.62||VOUT0_R_CR2/GP2_26||CPU.VOUT[0]_R_CR[2]/EMU4/GP2[26]||AD9||||I/O||||(1)
|-
| ||PLL_1V8||MTR||-||||O||||(1)
|-
| J2.64||VOUT0_R_CR3/GP2_27||CPU.VOUT[0]_R_CR[3]/GP2[27]||AB9||||I/O||||(1)
|-
| ||CORE_VDD||MTR||-||||O||||(1)
|-
| J2.66||"VOUT1_G_Y_YC3/GP3_7
|-
| GP3_23"||"CPU.VOUT[1]_G_Y_YC[3]/EMAC[1]_MRXD[6]/VIN[1]A_D[8]/GP3[7] (Y23)
|-
| EMAC[0]_MTCLK/VIN[1]B_D[0]/SPI[3]_SCS[3]n/I2C[2]_SDA/GP3[23]"||L24||||I/O||||(1)
|-
| ||CVDD_ARM||MTR||-||||O||||(1)
|-
| J2.68||VOUT1_R_CR9/GP3_19||CPU.VOUT[1]_R_CR[9]/EMAC[1]_MTXEN/VIN[1]A_D[20]/PATA_D[12]/UART5_TXD/GP3[19]||Y24||||I/O||||
|-
| J2.70||VOUT0_G_Y_YC2/GP2_24||CPU.VOUT[0]_G_Y_YC[2]/EMU3/GP2[24]||AH7||||I/O||||
|-
| J2.72||VOUT0_G_Y_YC3/GP2_25||CPU.VOUT[0]_G_Y_YC[3]GP2[25]||AH15||||I/O||||
|-
| J2.74||VOUT0_B_CB_C2/GP2_22||CPU.VOUT[0]_B_CB_C[2]/EMU2/GP2[22]||AG7||||I/O||||
|-
| J2.76||VOUT0_B_CB_C3/GP2_23||CPU.VOUT[0]_B_CB_C[3]/GP2[23]||AE15||||I/O||||
|-
| J2.78||MCA2_AFSX/GP0_11||CPU.MCA[2]_AFSX/GP0[11]||AA5||||I/O||||(1)
|-
| J2.78||CVDD_DSP||MTR||-||||O||||(1)
|-
| J2.80||MCA2_ACLKX/GP0_10||CPU.MCA[2]_ACLKX/GP0[10]||U6||||I/O||||(1)
|-
| J2.80||VDDQ_1V8||MTR||-||||O||||(1)
|-
| J2.82||DGND||DGND||-||||G||||
|-
| J2.84||MCA2_AHCLKX/GP0_9||CPU.AUD_CLKIN2/MCA[0]_AXR[9]/MCA[2]_AHCLKX/MCA[5]_AHCLKX/ATL_CLKOUT3/EDMA_EVT2/TIM3_IO/GP0[9]||H1||||I/O||||(1)
|-
| J2.84||CVDD_HDVICP||MTR||-||||O||||(1)
|-
| J2.86||MCA2_AXR0/GP0_12||CPU.MCA[2]_AXR[0]/SD0_DAT[6]/UART5_RXD/GP0[12]||N2||||I/O||||(1)
|-
| J2.86||DVDD||MTR||-||||O||||(1)
|-
| J2.88||MCA2_AXR1/GP0_13||CPU.MCA[2]_AXR[1]/SD0_DAT[7]/UART5_TXD/GP0[13]||V6||||I/O||||(1)
|-
| J2.88||DVDD_M||MTR||-||||O||||(1)
|-
| J2.90||MCA2_AXR2/GP0_14||CPU.MCA[2]_AXR[2]/MCA[1]_AXR[6]/SC0_VPPEN/TIM2_IO/GP0[14]||V5||||I/O||||
|-
| J2.92||MCA2_AXR3/GP0_15||CPU.MCA[2]_AXR[3]/MCA[1]_AXR[7]/TIM3_IO/GP0[15]||H2||||I/O||||
|-
| J2.94||JTAG_RTCK||CPU.RTCK||AD4||||I||||
|-
| J2.96||JTAG_TDO||CPU.TDO||AD4||||O||||
|-
| J2.98||JTAG_TCK||CPU.TCK||AC5||||I||||
|-
| J2.100||JTAG_TRSTn||CPU.TRSTn||AA4||||I||||
|-
| J2.102||MRST||SV.MR||6||||I||||
|-
| J2.104||VIN0A_VSYNC/UART5_CTS||CPU.VIN[0]A_VSYNC/UART5_CTSn/GP2[4]||AD20||||I/O||||
|-
| J2.106||I2C3_SCL||CPU.VOUT[1]_B_CB_C[8]/EMAC[1]_MRXD[4]/VIN[1]A_D[5]/I2C[3]_SCL/GP3[5]||AH26||||I/O||||
|-
| J2.108||I2C3_SDA||CPU.VOUT[1]_B_CB_C[9]/EMAC[1]_MRXD[5]/VIN[1]A_D[6]/I2C[3]_SDA/GP3[6]||AA24||||I/O||||
|-
| J2.110||EMU0||CPU.EMU0||AG8||||I/O||||
|-
| J2.112||DEVOSC_WAKE/TIM5_IO/GP1_7||CPU.DEVOSC_WAKE/SPI[1]_SCS[1]n/TIM5_IO/GP1[7]||W6||||I/O||||
|-
| J2.114||EEPROM_WP||EEPROM.||||||I/O||||
|-
| J2.116||DGND||DGND||-||||G||||
|-
| J2.118||EMU1||CPU.EMU1||AE11||||I/O||||
|-
| J2.120||VIN0A_DE/UART5_TXD||CPU.VIN[0]A_DE/VIN[0]B_HSYNC/UART5_TXD/I2C[2]_SDA/GP2[0]||AE21||||I/O||||
|-
| J2.122||VIN0A_FLD/UART5_RXD||CPU.VIN[0]A_FLD/VIN[0]B_VSYNC/UART5_RXD/I2C[2]_SCL/GP2[1]||AA20||||I/O||||
|-
| J2.124||USBP1||USB1.D+||||||A, I/O||||
|-
| J2.126||USBM1||USB1.D-||||||A, I/O||||
|-
| J2.128||UART3_RXD/SD1_POW||CPU.UART0_DCDn/UART3_RXD/SPI[0]_SCS[3]n/I2C[2]_SCL/SD1_POW/GP1[2]||AH4||||I/O||||
|-
| J2.130||UART3_CTSn||CPU.UART0_DTRn/UART3_CTSn/UART1_TXD/GP1[4]||AG2||||I/O||||
|-
| J2.132||VIN1A_D4/GP3_4||CPU.VOUT[1]_B_CB_C[7]/EMAC[1]_MRXD[3]/VIN[1]A_D[4]/UART3_TXD/GP3[4]||AC25||||I/O||||
|-
| J2.134||USBP2||USB2.D+||||||A, I/O||||
|-
| J2.136||USBM2||USB2.D-||||||A, I/O||||
|-
| J2.138||3.3V||+3V3||-||||S||||
|-
| J2.140||DGND||DGND||-||||G||||
|-
|
|}
==Legend and additional notes==
(1) Some pins support multiple routing options. Selected option is populated at manufacturing stage and can not be changed at later time.
