3,260
edits
Changes
→J2 odd pins (1 to 139)
==J2 odd pins (1 to 139)==
{| {{table}}
| align="center" style="background:#f0f0f0;"|'''Pin'''
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
| align="center" style="background:#f0f0f0;"|'''Supply Group'''
| align="center" style="background:#f0f0f0;"|'''Type'''
| align="center" style="background:#f0f0f0;"|'''Voltage'''
| align="center" style="background:#f0f0f0;"|'''Note'''
|-
| J2.1||3.3V||+3V3||-||||S||||
|-
| J2.3||DGND||DGND||-||||G||||
|-
| J2.5||GPMC_D0||CPU.GPMC_D[0]/BTMODE[0]||U26||||I/O||||
|-
| J2.7||GPMC_D2||CPU.GPMC_D[2]/BTMODE[2]||V27||||I/O||||
|-
| J2.9||GPMC_D4||CPU.GPMC_D[4]/BTMODE[4]||V26||||I/O||||
|-
| J2.11||GPMC_D6||CPU.GPMC_D[6]/BTMODE[6]||U25||||I/O||||
|-
| J2.13||CPU_NMIn||CPU.NMIn||H7||||I||||
|-
| J2.15||CPU_RESETn||CPU.RESETn||J5||||I||||
|-
| J2.17||VOUT1_G_Y_YC4/GP3_8||CPU.VOUT[1]_G_Y_YC[4]/EMAC[1]_MRXD[7]/VIN[1]A_D[9]/PATA_D[1]/GP3[8]||W22||||I/O||||
|-
| J2.19||SPI0_SCS1n/SD1_SDCD/SATA_ACT0_LED||CPU.SPI[0]_SCS[1]n/SD1_SDCD/SATA_ACT0_LED/EDMA_EVT1/TIM4_IO/GP1[6]||AE5||||I/O||||
|-
| J2.21||GPMC_A0||CPU.VOUT1_B_CB_C[2]/GPMC_A[0]/VIN[1]A_D[7]/HDMI_CEC/SPI[2]_D[0]/GP3[30]||AF28||||I/O||||
|-
| J2.23||GPMC_A2/SD2_DAT2||CPU.SD2_DAT[2]_SDRWn/GPMC_A[2]/GP2[6]||K27||||I/O||||
|-
| J2.25||GPMC_A4/SD2_DAT0||CPU.SD2_DAT[0]/GPMC_A[4]/GP1[14]||L26||||I/O||||
|-
| J2.27||GPMC_A6/CAM_D2||CPU.VOUT[1]_G_Y_YC[0]/CAM_D[2]/PATA_DA[2]/GPMC_A[6]/UART4_TXD/GP0[23]||AC18||||I/O||||
|-
| J2.29||GPMC_A8/CAM_D0||CPU.VOUT[1]_R_CR[0]/CAM_D[0]/PATA_DA[0]/GPMC_A[8]/UART4_RTSn/GP0[25]||AA22||||I/O||||
|-
| J2.31||GPMC_A10/CAM_VS||CPU.VOUT[1]_B_CB_C[0]/CAM_VS/PATA_IORDY/GPMC_A[10]/UART2_TXD/GP0[27]||AD23||||I/O||||
|-
| J2.33||VOUT0_FLD/CAM_PCLK/GPMC_A12/GP2_02||CPU.VOUT[0]_FLD/CAM_PCLK/GPMC_A[12]/UART2_RTSn/GP2[02]||AF18||||I/O||||
|-
| J2.35||3.3V||+3V3||-||||S||||
|-
| J2.37||DGND||DGND||-||||G||||
|-
| J2.39||GPMC_A14/I2C2_SDA||CPU.VOUT[1]_R_CR[3]/GPMC_A[14]/VIN[1]A_D[22]/HDMI_SDA/SPI[2]_SCLK/I2C[2]_SDA/GP3[21]||AG28||||I/O||||
|-
| J2.41||GPMC_A16||CPU.GPMC_A[16]/GP2[5]||AD27||||I/O||||
|-
| J2.43||GPMC_A18||CPU.GPMC_A[18]/TIM2_IO/GP1[13]||AE28||||I/O||||
|-
| J2.45||GPMC_A20||CPU.GPMC_A[20]/SPI[2]_SCS[1]n/GP1[15]||AD28||||I/O||||
|-
| J2.47||GPMC_A22||CPU.GPMC_A[22]/SPI[2]_D[1]/HDMI_CEC/TIM4_IO/GP1[17]||AB27||||I/O||||
|-
| J2.49||VOUT1_G_Y_YC6/GP3_10||CPU.VOUT[1]_G_Y_YC[6]/EMAC[1]_GMTCLK/VIN[1]A_D[11]/PATA_D[3]/GP3[10]||AH27||||I/O||||
|-
| J2.51||GPMC_CS0n||CPU.GPMC_CS[0]n/GP1[23]||T28||||I/O||||
|-
| J2.53||GPMC_CS2n||CPU.GPMC_CS[2]n/GPMC_A[24]/GP1[25]||M25||||I/O||||
|-
| J2.55||GPMC_CS4n||CPU.GPMC_CS[4]n/SD2_CMD/GP1[8]||P25||||I/O||||
|-
| J2.57||GPMC_WEn||CPU.GPMC_WEn||U28||||O||||
|-
| J2.59||GPMC_ADVn_ALE/GPMC_CS6n||CPU.GPMC_ADVn_ALE/GPMC_CS[6]n/TIM5_IO/GP1[28]||M26||||I/O||||
|-
| J2.61||GPMC_CLK/GPMC_CS5n/GPMC_WAIT1/CLKOUT1||CPU.GPMC_CLK/GPMC_CS[5]n/GPMC_WAIT[1]/CLKOUT1/EDMA_EVT3/TIM4_IO/GP1[27]||R26||||I/O||||
|-
| J2.63||VOUT1_G_Y_YC8/GP3_12||CPU.VOUT[1]_G_Y_YC[8]/EMAC[1]_MTXD[1]/VIN[1]A_D[13]/PATA_D[5]/GP3[12]||AE26||||I/O||||
|-
| J2.65||3.3V||+3V3||-||||S||||
|-
| J2.67||DGND||DGND||-||||G||||
|-
| J2.69||VOUT1_G_Y_YC9/GP3_13||CPU.VOUT[1]_G_Y_YC[9]/EMAC[1]_MTXD[2]/VIN[1]A_D[14]/PATA_D[6]/GP3[13]||AD26||||I/O||||
|-
| J2.71||VOUT1_R_CR8/GP3_18||CPU.VOUT[1]_R_CR[8]/EMAC[1]_MTXD[7]/VIN[1]A_D[19]/PATA_D[11]/UART5_RXD/GP3[18]||W23||||I/O||||
|-
| J2.73||VIN0A_D6/GP2_11||CPU.VIN[0]A_D[6]/GP2[11]||AH16||||I/O||||
|-
| J2.75||VIN0A_D7/GP2_12||CPU.VIN[0]A_D[7]/GP2[12]||AA11||||I/O||||
|-
| J2.77||VIN0A_D8_BD0/GP2_13||CPU.VIN[0]A_D[8]_BD[0]/GP2[13]||AB15||||I/O||||
|-
| J2.79||VIN0A_D9_BD1/GP2_14||CPU.VIN[0]A_D[9]_BD[1]/GP2[14]||AG9||||I/O||||
|-
| J2.81||VIN0A_D10_BD2/GP2_15||CPU.VIN[0]A_D[10]_BD[2]/GP2[15]||AH9||||I/O||||
|-
| J2.83||VIN0A_D12_BD4/GP2_17||CPU.VIN[0]A_D[12]_BD[4]/CLKOUT1/GP2[17]||AG17||||I/O||||
|-
| J2.85||GPMC_BE1n/GPMC_A24/EDMA_EVT1/TIM7_IO/GP1_30||CPU.GPMC_BE[1]n/GPMC_A[24]/EDMA_EVT1/TIM7_IO/GP1[30]||V28||||I/O||||
|-
| J2.87||SPI3_D1/GP3_16||CPU.VOUT[1]_R_CR[6]/EMAC[1]_MTXD[5]/VIN[1]A_D[17]/PATA_D[9]/SPI[3]_D[1]/GP3[16]||AA25||||I/O||||
|-
| J2.89||SPI3_D0/GP3_17||CPU.VOUT[1]_R_CR[7]/EMAC[1]_MTXD[6]/VIN[1]A_D[18]/PATA_D[10]/SPI[3]_D[0]/GP3[17]||V22||||I||||
|-
| J2.91||RSTOUTn||CPU.RSTOUTn_WD_OUTn||K6||||O||||
|-
| J2.93||VIN0A_HSYNC/UART5_RTS||CPU.VIN[0]A_HSYNC/UART5_RTSn/GP2[3]||AC20||||I/O||||
|-
| J2.95||TIM7_IO/GP0_28||CPU.MCA[5]_AXR[1]/MCA[4]_AXR[3]/TIM7_IO/GP0[28]||L6||||I/O||||
|-
| J2.97||EN_BCK2_LS||PMIC.GPIO7||L4||||O||||3.3V I/O Power Rail Enable
|-
| J2.99||SPI3_SCLKGP3_15||CPU.VOUT[1]_R_CR[5]/EMAC[1]_MTXD[4]/VIN[1]A_D[16]/PATA_D[8]/SPI[3]_SCLK/GP3[15]||AC26||||I/O||||
|-
| J2.101||3.3V||+3V3||-||||S||||
|-
| J2.103||DGND||DGND||-||||G||||
|-
| J2.105||JTAG_TDI||CPU.TDI||Y7||||I||||
|-
| J2.107||JTAG_TMS||CPU.TMS||AA7||||I/O||||
|-
| J2.109||PORSTn||CPU.PORn||F1||||I||||
|-
| J2.111||SPI3_SCS1n/GP3_14||CPU.VOUT[1]_R_CR[4]/EMAC[1]_MTXD[3]/VIN[1]A_D[15]/SPI[3]_SCS[1]n/GP3[14]||AG27||||I/O||||
|-
| J2.113||SPI3_D1/UART3_RTSn/GP2_29||CPU.VOUT[1]_HSYNC/EMAC[1]_MCOL/VIN[1]A_VSYNC/PATA_HDDIR/SPI[3]_D[1]/UART3_RTSn/GP2[29||AC24||||I/O||||
|-
| J2.115||EMAC0_PHY_LED_LINK/ACT||LAN.LED1||3||||||||
|-
| J2.117||EMAC0_PHY_LED_SPEED||LAN.LED2||2||||||||
|-
| J2.119||SPI3_D0/UART3_CTSn/GP2_30||CPU.VOUT[1]_VSYNC/EMAC[1]_MCRS/VIN[1]A_FLD/VIN[1]A_DE/SPI[3]_D[0]/UART3_CTSn/GP2[30]||AA23||||I/O||||
|-
| J2.121||UART3_TXD/SD1_SDWP||CPU.UART0_DSRn/UART3_TXD/SPI[0]_SCS[2]n/I2C[2]_SDA/SD1_SDWP/GP1[3]||AG4||||I/O||||
|-
| J2.123||UART3_RTSn||CPU.UART0_RIN/UART3_RTSn/UART1_RXD/GP1[5]||AF4||||I/O||||
|-
| J2.125||VIN1A_D3/GP3_3||CPU.VOUT[1]_B_CB_C[6]/EMAC[1]_MRXD[2]/VIN[1]A_D[3]/UART3_RXD/GP3[3]||AD25||||I/O||||
|-
| J2.127||ETH_CTTD||-||-||||||||
|-
| J2.129||ETH_TX-||LAN.TXN||28||||||||
|-
| J2.131||ETH_TX+||LAN.TXP||29||||||||
|-
| J2.133||ETH_RX+||LAN.RXP||31||||||||
|-
| J2.135||ETH_RX-||LAN.RXN||30||||||||
|-
| J2.137||ETH_CTRD||-||-||||||||
|-
| J2.139||DGND||DGND||-||||G||||
|-
|
|}
==J2 odd pins (1 to 139)==
==Legend and additional notes==
(1) Some pins support multiple routing options. Selected option is populated at manufacturing stage and can not be changed at later time.
