BoraEVB

Info Box Applies to Bora

Introduction

BoraEVB is a carrier board designed to host Bora.

Block Diagram

The following picture shows BoraEVB block diagram:

BoraEVB block diagram

Features

• 10/100/1000 Ethernet #0 (PS)
• 10/100/1000 Ethernet #1 (Routed through EMIO)
• 1x USB 2.0 OTG (MicroAB connector)
• 1x Serial port (RS232 DB9)
• 1x MicroSD
• External DDR3 SDRAM bank
  • This memory bank is connected to bank 35 - powered @ 1.5V - that is optimized at PCB level to interface such devices.
  • This bank is expressly available for peripherals and/or IPs implemented in FPGA fabric. This solution permits these blocks to work without impacting on Bora's DDR3 memory bandwidth. To access this bank, MIG (Memory Interface Generator) controller has to be implemented on PL.
    • MIG controller requires an external 200 MHz clock source.
• State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA
• XADC
  • Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connectors, instead of DDR3 memory.
• JTAG port
• Trace port
• Socket for DWM Wireless Module
• Digilent Pmod™ Compatible expansion connectors
• Headers for external for NAND flash and SPI NOR flash
• 2.54mm-pitch pin-strip connectors for Bora PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)
• Jumpers for voltage selection of the PL banks
• +12V power connector

Known limitations

Board version CS040713A has the following limitations:

Issue	Description
ETH0 interface	Mistake in the connection of the center tap pins. They should be separated from one another and connected through separate 0.1μF common-mode capacitors to ground (for further details (eg: connection and selection of the magnetics), please refer to the Micrel KSZ9031RNX datasheet).
External DDR3 bank	The DDR3 SDRAM bank is not supported in BELK 2.0.0
ETH1 interface	The additional Gigabit Ethernet interface (ETH1) is not supported in BELK 2.0.0

Connectors pinout

J1,J2 and J3

The pinout of the J1, J2 and J3 connectors of the Bora EVB is the same of the counterpart connectors on BORA module.

Power supply - J7

Power is provided through the J7 connector.

Pin#	Pin name	Function	Notes
1	VIN	Power supply	Nominal: +12V
2	DGND	Ground	-

POWER GOOD signals selector - J10

J10 is a 8-pin 4x2x2.54 pitch vertical header used for the selection - through jumpers - of the POWER GOOD options. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	BOARD_PGOOD	-	-
2, 4	3.3V_SOM	-	-
3	1.5V_POWER_GOOD	-	-
5	VREF_POWER_GOOD	-	-
6, 8	3.3V_SBY	-	-
7	1.8V_POWER_GOOD	-	-

The available configurations are:

• No jumpers mounted (DEFAULT)
• Jumper on 1-2 -> supply BOARD_PGOOD with 3.3V_SOM
• Jumper on 3-4 -> supply 1.5V_POWER_GOOD with 3.3V_SOM
• Jumper on 5-6 -> supply 1.5V_VREF_POWER_GOOD with 3.3V_SBY
• Jumper on 7-8 -> supply 1.8V_VREF_POWER_GOOD with 3.3V_SBY

BANK35, BANK13 VDDIO selector - J11

J11 is a 8-pin 4x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1, 5	3.3V	-	-
2, 4	VDDIO_BANK35	-	-
3	EVB_VDDQ_1V5	-	-
6, 8	VDDIO_BANK13	-	-
7	EVB_VDDIO_BANK13	-	-

The available configurations are:

1. Jumper on 1-2 -> supply VDDIO_BANK35 with 3.3V (requirerd when EVBB DDR3 device is used)
2. Jumper on 3-4 -> (Not Available) supply VDDIO_BANK35 with EVB_VDDQ_1V5 (requirerd when EVBB DDR3 device is used)
3. Jumper on 5-6 -> supply VDDIO_BANK13 with 3.3V
4. Jumper on 7-8 -> supply VDDIO_BANK35 with EVB_VDDIO_BANK13 (requirerd when TRACE is used)

The following rules must be observed:

• Because of a hardware limitation, VDDIO_BANK35 must be configured for 3.3V power supply (Jumper on 1-2).
• The configuration 1. (Jumper on 1-2) excludes 2. (Jumper on 3-4) (and viceversa)
• The configuration 3. (Jumper on 5-6) excludes 4. (Jumper on 7-8) (and viceversa)

The DEFAULT configuration is:

• Jumper on 1-2 (please note that this jumper must not be removed)
• Jumper on 5-6

Reset button - S6

S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)

Boot mode selection - S5

S5 is a dip-switch for the boot mode selection. The following table reports the available options and the related configurations:

	S5.1	S5.2	S5.3	S5.4	S5.5	S5.6	S5.7	S5.8
SPI-NOR	OFF	ON	OFF	ON	ON	ON	ON	OFF
SD-card	OFF	ON	OFF	ON	ON	OFF	ON	OFF
NAND	OFF	ON	OFF	ON	ON	OFF	ON	ON
JTAG	OFF	ON	OFF	ON	ON	ON	ON	ON

WatchDog Settings - S1, S2 and S3

S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the Bora module watchdog. For more details please refer to this page.

	S1.1	S1.2
WD_SET0 SOM default	OFF	OFF
WD_SET0 = '1'	ON	OFF
WD_SET0 = '0'	OFF	ON

	S2.1	S2.2
WD_SET1 SOM default	OFF	OFF
WD_SET1 = '1'	ON	OFF
WD_SET1 = '0'	OFF	ON

	S3.1	S3.2
WD_SET2 SOM default	OFF	OFF
WD_SET2 = '1'	ON	OFF
WD_SET2 = '0'	OFF	ON

Ethernet port #0 (ETH0) - J8

J8 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to the Bora integrated ethernet controller and PHY.

Pin#	Pin name	Function	Notes
1	ETH_TXRX0_P	-	-
2	ETH_TXRX0_M	-	-
3	ETH_TXRX1_P	-	-
4	ETH_TXRX2_P	-	-
5	ETH_TXRX2_M	-	-
6	ETH_TXRX1_M	-	-
7	ETH_TXRX3_P	-	-
8	ETH_TXRX3_M	-	-
9	3.3V_ETH0	-	-
10	GND_ETH0	-	-
11, 13	+3.3V	-	-
12	3.3V_ETH0_LED1	-	-
14	3.3V_ETH0_LED2	-	-

Ethernet port #1 (ETH1) - J9

J9 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to Micrel KSZ9031 PHY (Gigabit Ethernet Transceiver). This, in turn, is connected to PL's bank 34 via RGMII interface. This is an example of EMIO routing showing how to route PS's MAC signals via PL subsystem. Please note that, in case PL is not properly configured, this second Ethernet port will not work.

Pin#	Pin name	Function	Notes
1	ETH1_TXRX0_P	-	-
2	ETH1_TXRX0_M	-	-
3	ETH_TXRX1_P	-	-
4	ETH1_TXRX2_P	-	-
5	ETH1_TXRX2_M	-	-
6	ETH1_TXRX1_M	-	-
7	ETH1_TXRX3_P	-	-
8	ETH1_TXRX3_M	-	-
9	3.3V_ETH1	-	-
10	GND_ETH1	-	-
11, 13	+3.3V	-	-
12	3.3V_ETH1_LED1	-	-
14	3.3V_ETH1_LED2	-	-

JTAG

JTAG port is available as two different mechanical connectors:

• 2.00mm-pitch 7x2 header (Xilinx standard)
• 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
• This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.

JTAG XILINX - J13

J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1, 3, 5, 7, 9, 11, 13	DGND	-	-
2	3.3V	-	-
4	JTAG_TMS	-	-
6	JTAG_TCK	-	-
8	JTAG_TDO	-	-
10	JTAG_TDI	-	-
12	N.C.	-	-
14	JTAG_TRSTn	-	-

JTAG ARM - J18

J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	3.3V	-	-
2	3.3V	-	-
3, 11, 17, 19	N.C.	-	-
4, 6 ,8 ,10 ,12, 14, 16, 18, 20	DGND	-	-
5	JTAG_TDI	-	-
7	JTAG_TMS	-	-
9	JTAG_TCK	-	-
13	JTAG_TDO	-	-
15	JTAG_TRSTn	-	-

UART1 - J17

J17 is a standard DB9 connector that routes the signals coming from the RS232 transceiver that is connected to the PS MIO signals of the UART1 port.

Pin#	Pin name	Function	Notes
1, 6, 4, 9	N.C.	N.C.
2	UART_EXT_RX	Receive line	Connected to protection diode array
3	UART_EXT_TX	Transmit line	Connected to protection diode array
5	DGND	Ground
7, 8	N.C.	N.C.	Connected to protection diode array

USB OTG - J19

J19 is a standard USB MICRO AB connector. It is connected to the Bora USB 2.0 OTG peripheral. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	USB_OTG_VBUS	-	-
2	USBM1	-	-
3	USBP1	-	-
4	OTG_ID	-	-
5	USB_OTG_DGND	-	-
6, 7, 8, 9	USB_OTG_SHIELD	-	-

MicroSD - J21

J21 is a microSD memory card connector. It is connected to the Bora SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the BoraEVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	PS_SD0_DAT2	-	-
2	PS_SD0_DAT3	-	-
3	PS_SD0_CMD	-	-
4	3.3V	-	-
5	PS_SD0_CLK	-	-
6, 9, 10, 11, 12	DGND	-	-
7	PS_SD0_DAT0	-	-
8	PS_SD0_DAT1	-	-
3.3V	-		Pull up to 3.3V with 10K Ohm -

Trace Port - J22

J22 is a QSH–060–01–L–D–A 0,50 mm Hi-speed socket. It is connected to the Debug Trace Port. From the physical standpoint, trace port exploits the advanced routing of bank 13 signals implemented on Bora, combined with the possibility to select the I/O voltage of bank itself. Connector is compatible with ETMv1/ETMv3 specification. Please refer to http://www.lauterbach.com/frames.html?adetmmipi60.html for more details.

Please note that:

• JTAG and trace signals are EMIO routed to I/O of bank 13
• About tracing, several differents schemes are possible, depending of debug requirements. For example one might be interested in CPU-only tracing via PTM or fabric-only tracing via FTM. For more details please refer to Zynq TRM and these links:
  • http://www.lauterbach.com/frames.html?icretm.html
  • http://www.lauterbach.com/frames.html?icretb.html
  • http://www.lauterbach.com/frames.html?autofocus.html
  • http://www.xilinx.com/products/intellectual-property/1-24W427.htm.

The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	3.3V	-	-
2	JTAG_TMS	-	-
3	JTAG_TCK	-	-
4	JTAG_TDO	-	-
5	JTAG_TDI	-	-
6	JTAG_TRSTn	-	-
7, 8, 9, 10, 11, 18, 20, 22, 24 ,26, 28, 30, 32, 34, 36, 38, 40	N.C.	-	-
12	VDDIO_BANK13	-	-
13	IO_L15N_T2_DQS_13	-	-
14, 15, 16, ,42, 44, 46, 48, 50, 52, 54, 56, 57, 58, 59, 60	DGND	-	-
17	IO_L15P_T2_DQS_13	-	-
19	IO_L17N_T2_13	-	-
21	IO_L17P_T2_13	-	-
23	IO_L20N_T3_13	-	-
25	IO_L20P_T3_13	-	-
27	IO_L22N_T3_13	-	-
29	IO_L22P_T3_13	-	-
31	IO_L6N_T0_VREF_13	-	-
33	IO_L12N_T1_MRCC_13	-	-
35	IO_L12P_T1_MRCC_13	-	-
37	IO_L14N_T2_SRCC_13	-	-
39	IO_L14P_T2_SRCC_13	-	-
41	IO_L16N_T2_13	-	-
43	IO_L16P_T2_13	-	-
45	IO_L18N_T2_13	-	-
47	IO_L18P_T2_13	-	-
49	IO_L19N_T3_VREF_13	-	-
51	IO_L19P_T3_13	-	-
53	IO_L21N_T3_DQS_13	-	-
55	IO_L21P_T3_DQS_13	-	-
61, 62, 63, 64	DGND	-	-

DWM (DAVE Wifi/BT module) socket - J23

J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the DWM Wireless Module (optional) to the BoraEVB. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1, 2	5V	-	-
3, 4	3.3V	-	-
5, 6, 9, 10, 19	DGND	-	-
7	DWM_SD_CMD	-	-
8	DWM_SD_CLK	-	-
11	DWM_SD_DAT0	-	-
12, 14, 16, 18, 20, 22	N.C.	-	-
13	DWM_SD_DAT1	-	-
15	DWM_SD_DAT2	-	-
17	DWM_SD_DAT3	-	-
21	DWM_UART_RX	-	-
23	DWM_UART_CTS	-	-
24	DWM_BT_F5	-	-
25	DWM_UART_TX	-	-
26	DWM_BT_F2	-	-
27	DWM_UART_RTS	-	-
28	DWM_WIFI_IRQ	-	-
29	DWM_BT_EN	-	-
30	DWM_WIFI_EN	-	-

CAN - J24

J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1, 6, 7, 8, 9, 10	N.C.	-	-
2, 5	CAN_SHIELD	-	-
3	CAN_L	-	-
4	CAN_H	-	-

Touch screen - J25

J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoraEVB. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	TSC_YP	-	-
2	TSC_XP	-	-
3	TSC_YM	-	-
4	TSC_XM	-	-

LVDS - J26

J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1, 2	3.3V_LCD	-	-
3, 4, 7, 10, 13, 16, 19	DGND	Ground	-
5	LCD_LVDS_D0-	-	-
6	LCD_LVDS_D0+	-	-
8	LCD_LVDS_D1-	-	-
9	LCD_LVDS_D1+	-	-
11	LCD_LVDS_D2-	-	-
12	LCD_LVDS_D2+	-	-
15	LCD_LVDS_CLK+	-	-
17	LCD_P17	-	-
18	LCD_P18	-	-
20	LCD_P20	-	-
21,22	DGND	Ground	Shield

Pin strip connectors

ADC - JP10

JP10 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	IO_0_35	-	-
2, 4	VDDIO_BANK35	-	-
3, 6, 9, 12, 15	XADC_GND	-	-
5	ZYNQ_AD14P_35	-	Mount option
7	ZYNQ_AD14N_35	-	Mount option
8	ZYNQ_T0_VREF_35	-	Mount option
10	ZYNQ_T3_VREF_35	-	Mount option
11	ZYNQ_AD1P_35	-	Mount option
13	ZYNQ_AD1N_35	-	Mount option
14	ZYNQ_AD3P_35	-	Mount option
16	ZYNQ_AD3N_35	-	Mount option

SPI,NAND - JP13

JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1, 4, 9, 12	DGND	Ground	-
2	SPI0_CS0n	-	-
3	ZYNQ_SPI0_SCLK/NAND_IO1	-	-
5	ZYNQ_SPI0_DQ0/NAND_ALE	-	-
6	NAND_CS0/SPI0_CS1	-	-
7	ZYNQ_SPI0_DQ2/NAND_IO2	-	-
8	ZYNQ_SPI0_DQ1/NAND_WE	-	-
10	ZYNQ_SPI0_DQ3/NAND_IO0	-	-
11	ZYNQ_NAND_RD_B	-	-

Voltage Monitor - JP15

JP15 is a 12-pin 6x2x2.00 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	MON_VCCPLL	-	-
2	MON_3.3V	-	-
3	MON_XADC_VCC	-	-
4	MON_1V2_ETH	-	-
5	MON_FPGA_VDDIO_BANK35	-	-
6	MON_VDDQ_1V5	-	-
7	MON_FPGA_VDDIO_BANK34	-	-
8	MON_1.8V	-	-
9	MON_FPGA_VDDIO_BANK13	-	-
10	MON_1.0V	-	-
11	MON_1.8V_IO	-	-
12	DGND	Ground	-

Ethernet GPIO - JP18

JP18 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1, 2, 5, 6, 16	DGND	Ground	-
3	CLK125_NDO	-	-
4	ETH1_CLK125_NDO	-	-
7	ETH_MDC	-	-
8	ETH1_MDC	-	-
9	ETH_MDIO	-	-
10	ETH1_MDIO	-	-
11	ETH_INTn	-	-
12	ETH1_INTn	-	-
13	PS_MIO51_501	-	-
14	ETH1_RESETn	-	-
15	PS_MIO50_501	-	-

SPI,NAND - JP19

JP19 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1, 11, 12	DGND	Ground	-
2	NAND_BUSY	-	-
3	ZYNQ_NAND_CLE	-	-
4	NAND_IO3	-	-
5	NAND_IO4	-	-
6	NAND_IO5	-	-
7	NAND_IO6	-	-
8	NAND_IO7	-	-
9	CONN_SPI_RSTn	-	-
10	MEM_WPn	-	-

ADC - JP20

JP20 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	VDDIO_BANK35	-	-
2, 6, 11, 12	XADC_AGND	-	-
3	ZYNQ_AD0P_35	-	-
4	MON_XADC_VCC	-	-
5	ZYNQ_AD15P_35	-	-
7	ZYNQ_AD15N_35	-	-
8	XADC_VN_R	-	-
9	ZYNQ_AD2P_35	-	-
10	XADC_VP_R	-	-

I2C, BANK34 - JP21

JP21 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	EVB_1.8V	-	-
2	3.3V	-	-
3	PS_I2C0_DAT	-	-
4	I2C0_SDA	-	-
5	PS_I2C0_CK	-	-
6	I2C0_SCL	-	-
7, 8, 12, 13	DGND	Ground	-
9	IO_L6P_T0_34	CAN Transmitter	-
10	INA_ALERT	-	-
11	IO_L19P_T3_34	CAN Receiver	-
14	IO_L3P_T0_DQS_PUDC_B_34	-	-
15	IO_25_34	-	-
16	IO_0_34	-	-

Please note that:

• Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):
  • Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
  • resistive touch screen controller for LCD screen
  • consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption

FPGA, WatchDog, RTC, RST - JP22

JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	FPGA_INIT_B	-	-
2	RTC_32KHZ	-	-
3	FPGA_PROGRAM_B	-	-
4	RTC_RST	-	-
5	FPGA_DONE	-	-
6	RTC_INT/SQW	-	-
7, 8	DGND	Ground	-
9	WD_SET0	-	-
10	SYS_RSTn	-	-
11	WD_SET1	-	-
12	PORSTn	-	-
13	WD_SET2	-	-
14	MRSTn	-	-
15	PS_MIO15_500	-	-
16	CB_PWR_GOOD	-	-

Digilent Pmod™ Compatible headers

Please note that:

• Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:
  • http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812
  • http://www.maximintegrated.com/products/evkits/fpga-modules/
• Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector

Digilent Pmod™ Compatible - JP17

JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	PMOD_A0		-
2	PMOD_A4		-
3	PMOD_A1		-
4	PMOD_A5		-
5	PMOD_A2		-
6	PMOD_A6		-
7	PMOD_A3		-
8	PMOD_A7		-
9, 10	DGND	Ground	-
11, 12	3.3V		-

Digilent Pmod™ Compatible - JP23

JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin#	Pin name	Function	Notes
1	PMOD_B0	-	-
2	PMOD_B4	-	-
3	PMOD_B1	-	-
4	PMOD_B5	-	-
5	PMOD_B2	-	-
6	PMOD_B6	-	-
7	PMOD_B3	-	-
8	PMOD_B7	-	-
9, 10	DGND	Ground	-
11, 12	3.3V	-	-

Schematics

The following list details the schematic version/serial number association. For more details about the serial number composition, please refer to this page. The following serial numbers were manufactured according to the schematics version 2.4.0: S-EVBBxyz 00E5 S-EVBBxyz 00DF From S-EVBBxyz 00FC on (i.e. 00FC, 00FD, etc.) The following serial numbers were manufactured according to the schematics version 2.2.0: From S-EVBBxyz 00AC to S-EVBBxyz 00E4 From S-EVBBxyz 00E6 to 00DE From S-EVBBxyz 00E0 to 00FB.

U14 DDR3 chip can be populated alternatively with Micron MT41K64M16JT-15E or ISSI IS43TR16256BL-125KBLI

Release 2.4.0

• ORCAD: boraevb-2.4.0-BELK-dsn.zip
• PDF : boraevb_S.EVBB0000I1R_2.4.0.pdf

Release 2.2.1

• ORCAD: boraevb-2.2.1-BELK-dsn.zip
• PDF : boraevb_S.EVBB0000I1R_2.2.1.pdf

BOM

The following list details the BOM version/serial number association. For more details about the serial number composition, please refer to this page. The following serial numbers were manufactured according to the BOM version 2.4.0: S-EVBBxyz 00E5 S-EVBBxyz 00DF From S-EVBBxyz 00FC on (i.e. 00FC, 00FD, etc.). The following serial numbers were manufactured according to the BOM version 2.2.0: From S-EVBBxyz 00AC to S-EVBBxyz 00E4 From S-EVBBxyz 00E6 to 00DE From S-EVBBxyz 00E0 to 00FB.

Release 2.4.0

• BoraEVB: BORAEVB_S.EVBB0000I1R.2.4.0.CSV.zip

Release 2.2.0

• BoraEVB: boraevb-BOM_S.EVBB0000I1R.2.2.1.CSV_.zip

Layout

• boraevb-CS040713A_all_view.pdf

Mechanical

• DXF: boraevb_CS040713A.dxf.zip
• 3D: boraevb_CS040713A.emn