Difference between revisions of "Watchdog (Bora)"
DevWikiAdmin (talk | contribs) m |
|||
| Line 2: | Line 2: | ||
{{Applies To Bora}} | {{Applies To Bora}} | ||
{{InfoBoxBottom}} | {{InfoBoxBottom}} | ||
| + | ==Description and default configuration== | ||
| + | An external watchdog timer (Maxim MAX6373<ref name="MAX6373">https://www.maximintegrated.com/en/products/power/supervisors-voltage-monitors-sequencers/MAX6373.html</ref>) is connected to the PORSTn signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP. | ||
| + | Default mounting option is depicted in the following figure. | ||
| + | [[File:Bora-reset-scheme.png|thumb|center|700px|Watchdog timer default mounting option]] | ||
| + | WDI is connected to Zynq's PS_MIO15_500 I/O. This signal is available on Bora connectors as PS_MIO15_500 (J1.133). | ||
| − | + | The MAX6373 watchdog timer (WDT) is pin-selectable. It can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. As a default, they are configured as follows: | |
| + | *WD_SET2 = 1 | ||
| + | *WD_SET1 = 0 | ||
| + | *WD_SET0 = 0 | ||
| + | This set selects the option | ||
| + | *tDELAY = first edge | ||
| + | *tWD = 10s. | ||
| + | In other words, WDT is started when the first transition on WDI input is detected. Once started, its timeout period is 10s. The first transition of WDI input should be under software control. However, despite of the presence of 22kOhm pull-down on EX_WDT_REARM signal, during power-on sequence a spurious 0-to-1 transition may be observed on EX_WDT_REARM line. The voltage swing of this transition is variable, since it depends on the internal Zynq's pull-up value. In general, <u>WDT may be inadvertently started at power-up</u>, before software takes control of PS_MIO15_500 GPIO. <u>To avoid this situation, it is recommended to add a 2.2kOhm pull-down on carrier board, connected to the PS_MIO15_500 signal</u>. | ||
| − | + | In any case, when the watchdog is started, the software (bootloader/operating system) must take care of toggling the watchdog trigger pin (WDI) before the timeout expiration. | |
| − | + | ==Selecting different configurations== | |
| + | Since WD_SETx signals are routed externally, WDT configuration can be changed by optional circuitry implemented on the carrier board. Different solutions for the watchdog management can be implemented on the carrier board, depending on system requirements. The easiest circuit consists of additional pull-up/down resistors connected to WD_SETx pins in order to overrule default configuration. The exhaustive configurations options are listed in table 1 of reference <ref name="MAX6373"></ref>. | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | + | On request, PS_MIO15_500 can be disconnected from WDI (please contact Sales Department for more details). This configuration provides two independent signals (EX_WDT_REARM and PS_MIO15_500) that allow the implementation of customized solutions on carrier board. For example you may want to use the Zynq's System Watchdog Timer (SWDT) instead of MAX6373 to reset the system through PS_MIO15_500 that can be configured as SWDT reset. | |
| + | |||
Please note that on the BORAEVB carrier board, the watchdog is externally configured as disabled. | Please note that on the BORAEVB carrier board, the watchdog is externally configured as disabled. | ||
| + | |||
| + | ==References== | ||
Revision as of 08:31, 9 October 2015
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
Info Box
|
Description and default configuration[edit | edit source]
An external watchdog timer (Maxim MAX6373[1]) is connected to the PORSTn signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP.
Default mounting option is depicted in the following figure.
WDI is connected to Zynq's PS_MIO15_500 I/O. This signal is available on Bora connectors as PS_MIO15_500 (J1.133).
The MAX6373 watchdog timer (WDT) is pin-selectable. It can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. As a default, they are configured as follows:
- WD_SET2 = 1
- WD_SET1 = 0
- WD_SET0 = 0
This set selects the option
- tDELAY = first edge
- tWD = 10s.
In other words, WDT is started when the first transition on WDI input is detected. Once started, its timeout period is 10s. The first transition of WDI input should be under software control. However, despite of the presence of 22kOhm pull-down on EX_WDT_REARM signal, during power-on sequence a spurious 0-to-1 transition may be observed on EX_WDT_REARM line. The voltage swing of this transition is variable, since it depends on the internal Zynq's pull-up value. In general, WDT may be inadvertently started at power-up, before software takes control of PS_MIO15_500 GPIO. To avoid this situation, it is recommended to add a 2.2kOhm pull-down on carrier board, connected to the PS_MIO15_500 signal.
In any case, when the watchdog is started, the software (bootloader/operating system) must take care of toggling the watchdog trigger pin (WDI) before the timeout expiration.
Selecting different configurations[edit | edit source]
Since WD_SETx signals are routed externally, WDT configuration can be changed by optional circuitry implemented on the carrier board. Different solutions for the watchdog management can be implemented on the carrier board, depending on system requirements. The easiest circuit consists of additional pull-up/down resistors connected to WD_SETx pins in order to overrule default configuration. The exhaustive configurations options are listed in table 1 of reference [1].
On request, PS_MIO15_500 can be disconnected from WDI (please contact Sales Department for more details). This configuration provides two independent signals (EX_WDT_REARM and PS_MIO15_500) that allow the implementation of customized solutions on carrier board. For example you may want to use the Zynq's System Watchdog Timer (SWDT) instead of MAX6373 to reset the system through PS_MIO15_500 that can be configured as SWDT reset.
Please note that on the BORAEVB carrier board, the watchdog is externally configured as disabled.
