Difference between revisions of "Watchdog (Bora)"

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{{Applies To Bora}}
 
{{Applies To Bora}}
 
{{InfoBoxBottom}}
 
{{InfoBoxBottom}}
==Description and default configuration==
 
An external watchdog timer (WDT), Maxim MAX6373<ref name="MAX6373">https://www.maximintegrated.com/en/products/power/supervisors-voltage-monitors-sequencers/MAX6373.html</ref>), is connected to the PORSTn signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP.
 
  
Default mounting option is depicted in the following figure.
 
  
[[File:Bora-reset-scheme.png|thumb|center|700px|Watchdog timer default mounting option]]
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[[File:Bora-reset-scheme.png | 700px]]
  
WDI is connected to Zynq's PS_MIO15_500 I/O. This signal is available on Bora connectors as PS_MIO15_500 (J1.133).
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An external watchdog (Maxim MAX6373) is connected to the PORSTn signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP. By default WDI is connected to Zynq's PS_MIO15_500 I/O. WDI is available on Bora connectors as EX_WDT_REARM.
  
MAX6373 timeout is pin-selectable. It can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. By default, they are configured as follows:
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On request, PS_MIO15_500 can be disconnected from WDI (please contact Sales Department for more details). This configuration provides two independent signals (EX_WDT_REAM and PS_MIO15_500) that allow the implementation of customized solutions on carrier board. For example you may want to use the Zynq's System Watchdog Timer (SWDT) instead of MAX6373 to reset the system through PS_MIO15_500 that can be configured as SWDT reset.
*WD_SET2 = 1
 
*WD_SET1 = 1
 
*WD_SET0 = 0
 
This set selects the option (the exhaustive list of configurations options is descripted in table 1 of reference <ref name="MAX6373"></ref>):
 
*tDELAY = first edge
 
*tWD = 10s.
 
In other words, WDT is started when the first transition on WDI input is detected. Once started, its timeout period is 10s. The first transition of WDI input should be under software control. However, despite of the presence of 22kOhm pull-down, during power-on sequence a spurious 0-to-1 transition may be observed on WDI input. The voltage swing of this transition is variable, since it depends on the internal Zynq's pull-up value of PS_MIO15_500 pad. In general, <u>WDT may be inadvertently started at power-up</u>, before software takes control of PS_MIO15_500 GPIO. <u>To avoid this situation, it is recommended to add a 2.2kOhm pull-down on carrier board, connected to the PS_MIO15_500 signal</u>.
 
  
In any case, when the watchdog is started, the software (bootloader/operating system) must take care of toggling the watchdog trigger pin (WDI) before the timeout expiration.
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The MAX6373 watchdog timer is pin-selectable and the timer can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. As a default, the watchdog is configured on the BORA SOM to trigger at startup. Startup delay ends when WDI sees its first level transition. The default watchdog timeout period is 10 s.
  
==Selecting different configurations==
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The configuration can be changed by optional external circuitry implemented on the carrier board. There are two available solutions for the watchdog management to be implemented on the carrier board, depending on system requirements:
Since WD_SETx signals are routed externally, WDT configuration can be changed by optional circuitry implemented on the carrier board. Different solutions can be implemented on the carrier board, depending on system requirements. The easiest circuit consists of additional stronger pull-up/down resistors connected to WD_SETx pins in order to overrule default configuration. As MAX6373 allows to change the configuration during operation, more complex solutions can be implemented as well.
 
  
Please note that on the [[BoraEVB|BORAEVB]] carrier board, by default WDT is disabled via S1, S2 and S3 dip switches (WD_SET2=0, WD_SET1=1, WD_SET0=1).
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* adding the WD_SET[2..0] pull-up/pull-down resistors to be able to fully configure the device (in particular, the WD_SET[2..0] = 110 configuration keeps the watchdog timer disabled at startup)
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* adding a strong (2K2 Ohm) pull-down on the WDI/EX_WDT_REARM pin, to simply keep the watchdog inactive at startup
  
It is also worth mentioning that Zynq integrates a System Watchdog Timer (SWDT) that can optionally generates a reset pulse on PS_MIO15_500 pad if this is configured as SWDT reset. In case such a configuration is of interest, on request MAX6373 may not be populated. For more details about this option, please contact [mailto:sales@dave.eu Sales Department].
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When the watchdog is enabled, the software (bootloader/operating system) must take care of toggling the watchdog trigger pin (WDI) before the timeout expiration.
  
==References==
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Please note that on the BORAEVB carrier board, the watchdog is externally configured as disabled.

Revision as of 08:52, 24 July 2015

Info Box
Bora5-small.jpg Applies to Bora


Bora-reset-scheme.png

An external watchdog (Maxim MAX6373) is connected to the PORSTn signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP. By default WDI is connected to Zynq's PS_MIO15_500 I/O. WDI is available on Bora connectors as EX_WDT_REARM.

On request, PS_MIO15_500 can be disconnected from WDI (please contact Sales Department for more details). This configuration provides two independent signals (EX_WDT_REAM and PS_MIO15_500) that allow the implementation of customized solutions on carrier board. For example you may want to use the Zynq's System Watchdog Timer (SWDT) instead of MAX6373 to reset the system through PS_MIO15_500 that can be configured as SWDT reset.

The MAX6373 watchdog timer is pin-selectable and the timer can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. As a default, the watchdog is configured on the BORA SOM to trigger at startup. Startup delay ends when WDI sees its first level transition. The default watchdog timeout period is 10 s.

The configuration can be changed by optional external circuitry implemented on the carrier board. There are two available solutions for the watchdog management to be implemented on the carrier board, depending on system requirements:

  • adding the WD_SET[2..0] pull-up/pull-down resistors to be able to fully configure the device (in particular, the WD_SET[2..0] = 110 configuration keeps the watchdog timer disabled at startup)
  • adding a strong (2K2 Ohm) pull-down on the WDI/EX_WDT_REARM pin, to simply keep the watchdog inactive at startup

When the watchdog is enabled, the software (bootloader/operating system) must take care of toggling the watchdog trigger pin (WDI) before the timeout expiration.

Please note that on the BORAEVB carrier board, the watchdog is externally configured as disabled.