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{{AppliesToNaon}}
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===Overview===
DM8148 processor provides a rich video subsystem that integrates input ports. These are described in detail on chapter 12 of [http://www.ti.com/litvlit/pdf/sprugz8a| sprugz8] Technical Reference Manual].
Three video inputs are available:
===Main features===
The following is a list of VIN0/VIN1 main features:
* The HDVPSS supports two independently configurable external video input capture ports with up to165MHz.* Each video input capture port can be operated as one 24-bit mode to support RGB capture or 16-bitinput channel (with separate Y and Cb/Cr inputs) or two clock independent 8-bit input channels (withinterleaved Y/C data input).
* Support both embedded sync and discrete sync
* The video capture port channel supports de-multiplexing of both pixel-to-pixel and line-to-linemultiplexed streams.
* Up to 1920x1200@60 Hz (165 MHz) input data rate supports 16-bit mode input port.
* Each video capture port supports one scaler capable of both up and down scaling of onenon-multiplexed input stream (one of two 8-bit channel inputs or 16-bit channel input data). Note that ifthe source is from external video decoder/camera, only down scaling is supported.* Each video capture port supports one programmable color space conversion to convert between 24-bitRGB data and YCbCr data.
* The VIP supports data storage in RGB, 422, and 420 formats.
* Each video capture port channel supports chroma down-sampling (422 to 420) for any non-multiplexedinput data. The chroma down-sampling for multiplexed streams is done as memory to memoryoperations outside of HDVPSS on an individual frame data.
===Routing on Naon connectors===
The following tables summarizes lists which signals - referred to video input/output ports - are routed to Naon connectors and thus are available to user application. It is also useful to visualize potential issues due to the pads' multiplexing scheme.
{| class="wikitable" {{table}}
| align="center" style="background:#f0f0f0;"|'''PAD'''
| P26||||||B_CLK||||AVID||||||Y
|-
| Y22||||||A_CLK||||||||||NY
|-
| AE27||||||A_D23||||R_CR[2]||HPDET||||Y
| AF27||||||A_D21||||G_Y_YC[2]||SCL||||Y
|-
| Y24||||||A_D20||||R_CR[9]||||||NY
|-
| W23||||||A_D19||||R_CR[8]||||||NY
|-
| V22||||||A_D18||||R_CR[7]||||||Y
| AG27||||||A_D15||||R_CR[4]||||||Y
|-
| AD26||||||A_D14||||G_Y_YC[9]||||||NY
|-
| AE26||||||A_D13||||G_Y_YC[8]||||||NY
|-
| AF26||||||A_D12||||G_Y_YC[7]||||||NY
|-
| AH27||||||A_D11||||G_Y_YC[6]||||||NY
|-
| AG26||||||A_D10||||G_Y_YC[5]||||||NY
|-
| W22||||||A_D9||||G_Y_YC[4]||||||NY
|-
| Y23||||||A_D8||||G_Y_YC[3]||||||NY (1)
|-
| AF28||||||A_D7||||B_CB_C[2]||CEC||||Y
| AD25||||||A_D3||||B_CB_C[6]||||||Y
|-
| AF25||||||A_D2||||B_CB_C[5]||||||Y(1)
|-
| AG25||||||A_D1||||B_CB_C[4]||||||Y(1)
|-
| AH25||||||A_D0||||B_CB_C[3]||||||NY
|-
| R23||||||B_D7||||||||||N
| L24||||||B_D0||||||||||Y
|-
| AE24||||||A_HSYNC||||CLK||||||NY
|-
| AC24||||||A_VSYNC||||HSYNC||||||Y
|
|}
(1) Specific routing option is required. For more details please see [[Pinout (Naon)]].
Following is a brief summary of video input ports available on Naon connectors:
* VIN0A: fully available (24/16/8-bit)
* VIN0B: fully available (8-bit)
* VIN1A: fully available (D[23..0], 24/16/8-bit)
** '''Please note that, in order to use this port'''
**# '''I2C3 bus must be disabled.''' As a consequence keypad controller, EEPROM and touch screen controller are not available.
**# '''Gigabit Ethernet must be disabled.''' As a consequence only FastEthernet Interface is available and Ethernet Switch is working with only one port.
**# '''HDMI CEC must be disabled.''' Please note that CEC is optional on HDMI interface and is currently used only in consumer devices.
* VIN1B: not available
* CPI: fully available (up to 16-bit)
===Related links===
[[VIN0 to HDMI latency measurement (Naon)]]