Template:Processor subsytem

History
Version	Issue Date	Notes
X.Y.Z	Month Year	TBD
[TBD_link X.Y.Z]	Month Year	TBD
...	...	...

TBD: nella pagina vanno documentate le varie sezioni e documentate ad hoc a seconda del SoC (ad esempio per Bora va aggiunta la sezione PL)

Processor and memory subsystem

The heart of {{{nome-som}}} module is composed by the following components:

• TBD: SOC name SoC application processor
• Power supply unit
• DDR memory banks
• NOR and NAND flash banks
• TBD: SOM connector type connector with interfaces signals

This chapter shortly describes the main Axel Lite components.

Processor Info

Table: i.MX6 models comparison

Processor	# Cores	Clock	L2 Cache	DDR3	Graphics Acceleration	IPU	VPU	SATA-II
i.MX6 Solo	1	800 MHz 1 GHz	512 KB	32 bit @ 400 MHz	3D: Vivante GC880 2D: Vivante GC320 Vector: N.A.	1x	1x	N.A.
i.MX6 Dual	2	850 MHz 1 GHz 1.2 GHz	1 MB	64 bit @ 533 MHz	3D: Vivante GC2000 2D: Vivante GC320 Vector: Vivante GC335	2x	2x	Yes
i.MX6 Quad	4	850 MHz 1 GHz 1.2 GHz	1 MB	64 bit @ 533 MHz	3D: Vivante GC2000 2D: Vivante GC320 Vector: Vivante GC335	2x	2x	Yes

RAM memory bank

DDR3 SDRAM memory bank is composed by 4x 16-bit width chips resulting in a 64-bit combined width bank. The following table reports the SDRAM specifications:

CPU connection	Multi-mode DDR controller (MMDC)
Size min	512 MB
Size max	4 GB
Width	64 bit
Speed	533 MHz

NOR flash bank

NOR flash is a Serial Peripheral Interface (SPI) device. This device is connected to the eCSPI channel 5 and by default it acts as boot memory. The following table reports the NOR flash specifications:

CPU connection	eCSPI channel 5
Size min	8 MB
Size max	64 MB
Chip select	ECSPI5_SS0
Bootable	Yes

NAND flash bank

On board main storage memory is a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. Optionally, it can act as boot peripheral. The following table reports the NAND flash specifications:

CPU connection	Raw NAND flash controller
Page size	512 byte, 2 kbyte or 4 kbyte
Size min	128 MB
Size max	2 GB
Width	8 bit
Chip select	NANDF_CS0
Bootable	Yes

eMMC flash bank

CPU connection	SDIO
Page size	xxxxxx
Size min	xxx MB
Size max	xxx GB
Width	xx bit
SDHC
Bootable	Yes

Memory map

For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX Applications Processor Reference Manual.

Power supply unit

{{{nome-som}}} embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.

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[[Category:{{{nome-som}}}]]