Difference between revisions of "Template:Pinout"
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The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to {{{nome-som}}} pinout specifications. See the images below for reference: | The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to {{{nome-som}}} pinout specifications. See the images below for reference: | ||
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[[File:{{{nome-som}}}-top.png|500px|thumb|{{{nome-som}}} TOP view|none]] | [[File:{{{nome-som}}}-top.png|500px|thumb|{{{nome-som}}} TOP view|none]] | ||
[[File:{{{nome-som}}}-bottom.png|500px|thumb|{{{nome-som}}} BOTTOM view|none]] | [[File:{{{nome-som}}}-bottom.png|500px|thumb|{{{nome-som}}} BOTTOM view|none]] | ||
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===Pinout table naming conventions === | ===Pinout table naming conventions === |
Revision as of 13:04, 21 November 2020
History | |||
---|---|---|---|
Version | Issue Date | Notes | |
X.Y.Z | Month Year | TBD | |
[TBD_link X.Y.Z] | Month Year | TBD | |
... | ... | ... |
TBD: modificare la tabella seguente con le caratteristiche dei pin del SOM
TBD: modificare le due tabelle ODD e EVEN con la mappa completa dei pins
TBD: nella tabella naming conventions, inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)
Contents
Connectors and Pinout Table[edit source]
Connectors description[edit source]
In the following table are described all available connectors integrated on [[{{{nome-som}}}]]:
Connector name | Connector Type | Notes | Carrier board counterpart |
---|---|---|---|
J1 | SODIMM DDR3 edge connector 204 pin | TE Connectivity 2-2013289-1 | |
Jxx | TBD | TBD | TBD |
Jxx | TBD | TBD | TBD |
Jxx | TBD | TBD | TBD |
Jxx | TBD | TBD | TBD |
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to {{{nome-som}}} pinout specifications. See the images below for reference:
[[File:{{{nome-som}}}-top.png|500px|thumb|{{{nome-som}}} TOP view|none]] [[File:{{{nome-som}}}-bottom.png|500px|thumb|{{{nome-som}}} BOTTOM view|none]]
Pinout table naming conventions[edit source]
This chapter contains the pinout description of the {{{nome-som}}} module, grouped in two tables (odd and even pins) that report the pin mapping of the TBD: connector type {{{nome-som}}} connector.
Each row in the pinout tables contains the following information:
Pin | Reference to the connector pin |
Pin Name | Pin (signal) name on the {{{nome-som}}} connectors |
Internal connections |
Connections to the {{{nome-som}}} components
|
Ball/pin # | Component ball/pin number connected to signal |
Voltage | I/O voltage levels |
Type | Pin type:
|
Notes | Remarks on special pin characteristics |
Pin MUX alternative functions | Muxes:
The number of functions depends on platform |
Pinout Table ODD pins declaration[edit source]
Pin | Pin Name | Internal Connections | Ball/pin # | Voltage domain | Type | Notes | Alternative Functions | |
---|---|---|---|---|---|---|---|---|
J2.69 | SD2_CMD | CPU.SD2_CMD | F19 | AXEL_IO_3V3 | IO | Notes | Pin ALT-0 | SD2_CMD |
Pin ALT-1 | ECSPI5_MOSI | |||||||
Pin ALT-2 | KEY_ROW5 | |||||||
Pin ALT-3 | AUD4_RXC | |||||||
Pin ALT-5 | GPIO1_IO11 |
Pinout Table EVEN pins declaration[edit source]
Pin | Pin Name | Internal Connections | Ball/pin # | Voltage domain | Type | Notes | Alternative Functions | |
---|---|---|---|---|---|---|---|---|
J2.69 | SD2_CMD | CPU.SD2_CMD | F19 | AXEL_IO_3V3 | IO | Notes | Pin ALT-0 | SD2_CMD |
Pin ALT-1 | ECSPI5_MOSI | |||||||
Pin ALT-2 | KEY_ROW5 | |||||||
Pin ALT-3 | AUD4_RXC | |||||||
Pin ALT-5 | GPIO1_IO11 |
[[Category:{{{nome-som}}}]]