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{{AppliesToMito8M}}
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{{WarningMessage|text=This technical note was validated against specific versions of hardware and software. It What is described here may not work with other versions.}}
[[Category:MISC-AN-TN]]
[[Category:MISC-TN]]
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== History ==
{| class="wikitable" border="1"
!Version
!Date
!Notes
|-
|1.0.0
|January 2020
|First public release
|}
==Introduction==
Mito8M is the first DAVE Embedded Systems' product based on a core implementing the [https://en.wikipedia.org/wiki/ARM_architecture#64/32-bit_architecture ARMv8-A] architecture. Traditionally, ARM cores that are based on 32-bit [https://en.wikipedia.org/wiki/ARM_architecture#AArch32 ARMv7-A] architecture exhibit a limited RAM bandwidth even if they are coupled with 64-bit witdh SDRAM banks. When dealing with computationally heavy tasks, this factor may turn out to be a severe bottleneck limiting the overall performance.
Beside an intrinsic increased computational power, ARMv8-A-based SoC's are expected to improve significantly RAM bandwidth as well. This technical note (TN for short) illustrates several benchmarking tests that were run on Mito8M SoM, which is built upon [https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i.mx-applications-processors/i.mx-8-processors/i.mx-8m-family-armcortex-a53-cortex-m4-audio-voice-video:i.MX8M NXP i.MX8M Quad].
==Testbed general configuration==
This section illustrates the configuration settings common to all the tests performed.
==Results==SoC and SDRAM bank organization===={| class="wikitable"|+!!!Mito8M!|-| rowspan="2" |SoC|SoC|NXP i.MX8M Quad||-|ARM frequency[MHz]|800||-| rowspan="5" |SDRAM|Type|LPDDR4||-|Frequency[MHz]|1600||-|Bus witdth[bit]|32||-|Theoretical bandiwidth[Gb/s]|102.4||-|Size[MB]|3072||} ====Software configuration==== * Linux kernel: 4.14.98* Architecture: aarch64* Governor: userspace @ 800 MHz<pre class="board-terminal">root@Mito8M:~# echo userspace > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governorroot@Mito8M:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governoruserspaceroot@Mito8M:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq800000</pre>
GCC
<pre class="board-terminal">
armbian@Mito8M:~/devel/lmbench$ gcc -v
Using built-in specs.
Thread model: posix
gcc version 8.3.0 (Debian 8.3.0-6)
</pre>
==Results==
This section details the results that were achieved by the different benchmarks
===General configuration===
===Testbed #1===
{| class="wikitable"
|}
==Test programsDetailed testing procedures==This sections details how the benchmarks were configured and run on the testbed.
===STREAM===
</pre>
<syntaxhighlight lang="makefile" line='"line'">
armbian@Mito8M:~/devel/STREAM$ cat Makefile
CC = gcc
-------------------------------------------------------------
</pre>
==Useful links==
*[https://www.cs.virginia.edu/stream/ STREAM benchmark]
*[http://lmbench.sourceforge.net/ LM Bench benchmark]
*[https://panthema.net/2013/pmbw/ pmbw benchmark ]
*Joshua Wyatt Smith and Andrew Hamilton, [http://inspirehep.net/record/1424637/files/1719033_626-630.pdf Parallel benchmarks for ARM processors in the highenergy context]
*T Wrigley, G Harmsen and B Mellado, [http://inspirehep.net/record/1424631/files/1719033_275-280.pdf Memory performance of ARM processors and itsrelevance to High Energy Physics]
*G. T. Wrigley, R. G. Reed, B. Mellado, [http://inspirehep.net/record/1424637/files/1719033_626-630.pdf Memory benchmarking characterisation of ARM-based SoCs]