→Examples of valid combinations for Zynq 7015-based SOMs
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{{Applies To BoraX}}
{{Applies To BoraLite}}
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[[File:Boraxevb{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SoM when it is sold with BoraX. When it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead.png|650px|frameless|border]]
Nevertheless, BoarX can host different models of BoraX and Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
Bora BORA Xpress EVB is a carrier board designed to host [[BoraXpress SOMBORA_Xpress_SOM|Bora BORA Xpress system-on-module]]. [[File:BoraXEVB-01.png|500px|frameless|border]]
==Block Diagram==
The following picture shows Bora BORA Xpress EVB block diagram: [[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]===Configurable routing options===FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture. For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]]. ====BoraX====[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]
====Bora Lite====[[File:BoraxevbBoralite-block_diagramboraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]]
== Features ==
| LCD_BKLT_PWM I/O voltage
| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.
|-
| FMC connector
| For the [[Product_serial_number|serial numbers]] included in the range EVBBX0000C0R00A0 - EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.
|-
|}
== Connectors pinout ==
=== J1 ,J2 and J3 ===The pinout of the J1 connector of the Bora Xpress EVB is the same of the J1 connector on BORA Xpress module=== , J2 ===The pinout of the J2 connector of the Bora Xpress EVB is the same of the J2 connector on BORA Xpress module=== and J3 ===The pinout of the J3 connector connectors of the Bora Xpress EVB is the same of the J3 connector [[Pinout (BORAXpress)|counterpart connectors on BORA Xpress module]].
=== Power supply - JP2 ===
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[:Category:BoraLite |BoraLite]] SOM module
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.
For more details please refer to [[Watchdog (BORAXpress)|this page]].
{| class="wikitable"
|-
! !! S1.1 !! S1.2
|-
| WD_SET0 SOM default || OFF || OFF
|-
| WD_SET0 = '1' || ON || OFF
|-
| WD_SET0 = '0' || OFF || ON
|}
{| class="wikitable"
|-
! !! S2.1 !! S2.2
|-
| WD_SET1 SOM default || OFF || OFF
|-
| WD_SET1 = '1' || ON || OFF
|-
| WD_SET1 = '0' || OFF || ON
|}
{| class="wikitable"
|-
! !! S3.1 !! S3.2
|-
| WD_SET2 SOM default || OFF || OFF
|-
| WD_SET2 = '1' || ON || OFF
|-
| WD_SET2 = '0' || OFF || ON
|}
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
=== JTAG ===
JTAG port is available as two different mechanical connectors:
* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
=== BANK13 VDDIO selector = JTAG XILINX - JP25 J13 ====JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
|4 || LDO_B13_800mVJTAG_TMS|| adds +800mV to VDDIO_BANK13 - || -
|-
|6 || LDO_B13_400mVJTAG_TCK|| adds +400mV to VDDIO_BANK13 - || -
|-
|8 || LDO_B13_200mVJTAG_TDO|| adds +200mV to VDDIO_BANK13 - || -
|-
|10 || LDO_B13_100mVJTAG_TDI|| adds +100mV to VDDIO_BANK13 - || -
|-
|12 || LDO_B13_50mVN.C.|| adds +50mV to VDDIO_BANK13 - || -
|-
|1, 3, 5, 7, 9, 11 14 || DGNDJTAG_TRSTn|| - || -
|-
|}
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mVThe DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 === BANK35 VDDIO selector = JTAG ARM - JP27 J18 ====JP27 J18 is a 1220-pin 6x2x210x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable"
The jumper configurations are:# No jumpers installed === UART1 -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mVJ17 ===
The DEFAULT configuration J17 is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above a standard DB9 connector that routes the signals coming from the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35Please note RS232 transceiver that:* By default VDDIO_BANK35 is supplied by VADJ Regulator=== VADJ VDDIO selector - JP28 ===JP28 is a 12-pin 6x2x2.54 pitch vertical header used for connected to the selection - through jumpers - PS MIO signals of the bank supply voltagesUART1 port. The following table reports the pinout of the connector:
The jumper configurations are:# Jumper on 1=== USB OTG -2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2VJ19 ===
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The DEFAULT configuration isfollowing table reports the pinout of the connector:# Jumper on 5-6 -> supply VADJ with 1.8V
=== JTAG ===JTAG port is available as two different mechanical connectors:* 2.00mm-pitch 7x2 header (Xilinx standard)* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.* JTAG on Bora Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.==== JTAG XILINX - J13 ====J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:{| class="wikitable"
==== JTAG ARM MicroSD - J18 =J21 ===J18 J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a 20bidirectional 1.8V/3.3V voltage-pin 10x2x2level translator mounted on the BORA Xpress EVB.54 pitch vertical headerLevel shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
|15 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
=== UART1 DWM (DAVE Wifi/BT module) socket - J17 J23 === J17 J23 is a standard DB9 52991-0308 connector that routes type (30 pins, vertical, 0.50mm picth). This socket connects the signals coming from [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the RS232 transceiver that is connected to BORA Xpress EVB. The following table reports the PS MIO signals pinout of the UART1 port.connector:
|7, 8|N.C.|N.C.DWM_SD_CLK |Connected to protection diode array| - || -
|-
|}=== USB OTG 11 ||DWM_SD_DAT0 || - J19 ===J19 is a standard USB MICRO AB connector. It is connected to the Bora Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:{| class="wikitable" | -
=== MicroSD CAN - J21 J24 === J21 J24 is a microSD memory card connector10-pin 5x2x2. It is 54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the Bora Xpress SOM through a bidirectional 1CAN interface.8V/3This 2.3V voltage5mm-level translator mounted on the Bora Xpress EVB. Level shifter pitch header is required because MIO signals are 1.8Vcompatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
|} === Touch screen - J25===J25 is a ZIF 4 ||3-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB.3VThe following table reports the pinout of the connector: {||| - || -class="wikitable"
|13 4 |3.3V|TSC_XM || - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
=== DWM (DAVE Wifi/BT module) socket LVDS - J23 J26 ===J23 J26 is a 52991vertical double row straight 20-0308 connector type (30 pinspin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, verticalZynq does not implement an LCD controller, 0however this can be integrated in FPGA fabric as shown by this example: https://wiki.50mm picth)analog. This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the Bora Xpress EVBcom/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
|26 ||DWM_BT_F2 || } === FPGA Mezzanine Card (FMC) Connector - || J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.|-|27 ||DWM_UART_RTS || - || -Please note that BoraXpress EVB FMC Connector is:|-* fully compliant to FMC LPC|28 ||DWM_WIFI_IRQ || - || -* partially compliant to FMC HPC because HPC side is not fully populated.|-|29 ||DWM_BT_EN || The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB- || FMC-routing.zip|-link]] a spreadsheet providing the same information is available for download.|30 ||DWM_WIFI_EN || - || -|For more information about I/O voltage of single-ended signals available on FMC connector, please refer to [[#PL's I/O voltage selections|}this section]].
=== CAN - J24 = HPC Row A ====J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
|}=== Touch screen - J25===J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the Bora Xpress EVB. The following table reports the pinout of the connector:{A5||DGND||GND|| class="wikitable"
|}=== LVDS - J26 ===J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:{A11||MGTxRXN3||DP3_M2C_N|| class="wikitable"
|}=== FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because of FMC HPC side not fully populated==== HPC Row A ===={A26||MGTxTXP2||DP2_C2M_P|| class="wikitable"
| K14K40||NC<span style="color:#ff0000">not connected</span>||HA10_NVIO_B_M2C|||} === Pin strip connectors === ==== SPI,NAND - JP13 ==== JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
|-
| K15||DGND||GND||!Pin# !Pin name!Function!Notes
|-
| K161, 4, 9, 12 ||NCDGND ||HA17_P_CCGround ||-
|-
| K172 ||NCSPI0_CS0n ||HA17_N_CC- ||-
|-
| K183 ||DGNDZYNQ_SPI0_SCLK/NAND_IO1 ||GND- ||-
|-
| K195 ||NCZYNQ_SPI0_DQ0/NAND_ALE ||HA21_P- ||-
|-
| K206 ||NCNAND_CS0/SPI0_CS1 ||HA21_N- ||-
|-
| K217 ||DGNDZYNQ_SPI0_DQ2/NAND_IO2 ||GND- ||-
|-
| K228 ||NCZYNQ_SPI0_DQ1/NAND_WE ||HA23_P- ||-
|-
| K2310 ||NCZYNQ_SPI0_DQ3/NAND_IO0 ||HA23_N- ||-
|-
| K2411 ||DGNDZYNQ_NAND_RD_B ||GND- ||-
|-
| K25||NC||HB00_P_CC|} ==== Voltage Monitor - JP15 ==== JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|class="wikitable"
=== Pin strip connectors ======= SPI,NAND Ethernet GPIO - JP13 JP18 ==== JP13 JP18 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
==== Voltage Monitor SPI,NAND - JP15 JP19 ==== JP15 JP19 is a 1612-pin 8x2x26x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
==== Ethernet GPIO FPGA, WatchDog, RTC, RST - JP18 JP22 ====JP18 JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
==== SPI,NAND AUX PINs - JP19 JP29 ====JP19 JP29 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|14 || XADC_VP_R || - || -|-|15 || INA_ALERT || - || -|-|} Please note that: * Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption ==== FPGA, WatchDogADC - JP30, RTCJP31, RST - JP22 JP32 ====JP22 is a JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following table tables reports the pinout of the connectorconnectors:
Please note that:* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption==== ADC - JP30, JP31, JP32 ====JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors:JP30:
JP31=== Digilent Pmod™ Compatible headers === Please note that:* Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812** http://www.maximintegrated.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector ==== Digilent Pmod™ Compatible - JP17 ==== JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable" |-
!Pin#
!Pin name
!Notes
|-
|1 || FPGA_BANK35_AD5N PMOD_A0 || AD5_N || Mount option-
|-
|4 2 || FPGA_BANK35_AD6P PMOD_A4 || AD6_P || Mount option-
|-
|5 3 || FPGA_BANK35_AD7P PMOD_A1 || AD7_P || Mount option-
|-
|6 4 || FPGA_BANK35_AD6N PMOD_A5 || AD6_N || Mount option-
|-
|7 5 || FPGA_BANK35_AD7N PMOD_A2 || AD7_N || Mount option-
|-
|10 6 || FPGA_BANK35_AD8P PMOD_A6 || AD8_P || Mount option-
|-
|11 7 || FPGA_BANK35_AD9P PMOD_A3 || AD9_P || Mount option-
|-
|12 8 || FPGA_BANK35_AD8N PMOD_A7 || AD8_N || Mount option-
JP32==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_BANK35_AD11P PMOD_B0 || AD11_P - || Mount option-
|-
|2 || FPGA_BANK35_AD10N PMOD_B4 || AD10_N - || Mount option-
|-
|3 || FPGA_BANK35_AD11N PMOD_B1 || AD11_N - || Mount option-
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
=== Digilent Pmod™ Compatible headers =PL's I/O voltage selections==PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:*'''each bank must be powered even if none of its I/Os is used'''*'''voltage selection must be done before powering up the board'''.
Please note thatThe following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies. {| class="wikitable" style="text-align: center;"* Digilent Pmod™ Interface Specification ! rowspan="2" |SoM! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34! colspan="2" style="text-align: center; font-weight: bold;" | Bank #13! colspan="2" style="text-align: center; font-weight: bold;" | Bank #35|-| style="text-align: center; font- defined by Digilent Inc. weight: bold;" | Type [1]| style="text- allows to quickly connect several prealign: center; font-built weight: bold;" | I/O modules to PLvoltage setting| style="text-align: center; font-weight:bold;" | Type [1]** http| style="text-align: center; font-weight:bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/wwwO voltage setting|-| rowspan="2" |BoraX| style="text-align: center;" | 7015(CLG485 package)| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|-| style="text-align: center;" | 7030(SBG485 package)| style="text-align: center;" | HP(1.digilentinc2 - 1.com8V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined|-| rowspan="2" |Bora Lite| style="text-align: center;" | 7007S/Products/Catalog7010(CLG400 package)| style="text-align: center;" | HR(1.2 - 3.cfm?NavPath3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2,401&Cat- 3.3V)| style=9&CFID"text-align: center;" | User defined| style=3145471&CFTOKEN"text-align: center;" | HR(1.2 - 3.3V)| style=69407812"text-align: center;" | User defined|-** http| style="text-align:center;" | 7014S//www7020(CLG400 package)| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.maximintegrated2 - 3.com/products/evkits/fpga3V)| style="text-modules/align: center;" | User defined|}[1]*HR = High Range* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector HP = High Performance
==== Digilent Pmod™ Compatible - JP17 =BoraXEVB voltage selection jumpers===BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''.
JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the pinout same for all of the connector:BoraX models'''. Please refer to the following sections for more details.
Even if PL's banks are independent, default configuration of BoraXEVB is such that*bank 34 and bank 35 have the same supply voltage*this voltage is selected via JP28.This configuration is in accordance with default routing of signals used for FMC connector.====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)===={| class="wikitable" style="text-align: center;"|+Bank #13 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP25.1-2! style="text-align: center; font-weight: bold;" | JP25.3-4! style="text-align: center; font-weight: bold;" | JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" | JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open
|style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|} {| class="wikitable" style="text-align: center;"|+Bank #34 (HP)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP28.1-2! style="text-align: center; font-weight: bold;" | JP28.3-4! style="text-align: center; font-weight: bold;" | JP28.5-6! style="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" | JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} ====Examples of valid combinations for Zynq 7015-based SOMs===={| class="wikitable" style="text-align: center;"|+Bank #13 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP25.1-2! style="text-align: center; font-weight: bold;" | JP25.3-4! style="text-align: center; font-weight: bold;" | JP25.5-6! style="text-align: center; font-weight: bold;" | JP25.7-8! style="text-align: center; font-weight: bold;" | JP25.9-10! style="text-align: center; font-weight: bold;" | JP25.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} {| class="wikitable" style="text-align: center;"|+Bank #35 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP27.1-2! style="text-align: center; font-weight: bold;" | JP27.3-4! style="text-align: center; font-weight: bold;" | JP27.5-6! style="text-align: center; font-weight: bold;" | JP27.7-8! style="text-align: center; font-weight: bold;" | JP27.9-10! style="text-align: center; font-weight: bold;" | JP27.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open |} {| class="wikitable" style="text-align: center;"|+Bank #34 (HR)|-! style="text-align: center; font-weight: bold;" | Nominal voltage [V]! style="text-align: center; font-weight: bold;" | JP28.1-2! style="text-align: center; font-weight: bold;" | JP28.3-4! style="text-align: center; font-weight: bold;" | JP28.5-6! style="text-align: center; font-weight: bold;" | JP28.7-8! style="text-align: center; font-weight: bold;" | JP28.9-10! style="text-align: center; font-weight: bold;" | JP28.11-12|-| style="text-align: center;" | 1.2| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open|-| style="text-align: center;" | 1.5| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 1.8| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 2.5| style="text-align: center;" | open| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|-| style="text-align: center;" | 3.3| style="text-align: center;" | '''closed'''| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open| style="text-align: center;" | open|} ====Advanced information about voltage selection connectors========= Bank 13 VDDIO selection connector (JP25) =====JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B13_1V6|| adds +1.6V to VDDIO_BANK13 || -|-|4 || LDO_B13_800mV|| adds +800mV to VDDIO_BANK13 || -|-|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -|-|8 || LDO_B13_200mV|| adds +200mV to VDDIO_BANK13 || -|-|10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -|-|12 || LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 ===== Bank 35 VDDIO selection connector (JP27) =====JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -|-|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -|-|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -|-|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -|-|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -|-|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. ===== Bank 34 and VADJ VDDIO selection connector (JP28) =====JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -|-|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -|-|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -|-|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -|-|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -|-|12 || RFU|| Reserved || -|-|1, 3, 5, 7, 9, 11 || DGND|| - || -|-|} The jumper configurations are:# Jumper on 1-2 -> supply VADJ with 3.3V# Jumper on 3-4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2V The default configuration is:# Jumper on 5-6 -> supply VADJ with 1.8V ==SoM's signals mapping=====Bora Lite===As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here '''it is assumed to use an adapter with default mounting options'''. {| class="wikitable"|+! colspan="2" |SoM's signal! colspan="6" |Routing options at carrier board level|-! rowspan="2" |Bank! rowspan="2" |Name! colspan="3" |Option #1(default)! colspan="3" |Option #2|-!Name!Pin!Note!Name!Pin!Note|-| rowspan="54" |34| rowspan="2" |IO_0_34| rowspan="2" |'''IO_0_VRN_34'''|J31.2|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27D.H2|FMC conn.|-| rowspan="2" |IO_25_34| rowspan="2" |'''IO_25_VRP_35'''|J31.4|Header| rowspan="2" || rowspan="2" || rowspan="2" ||-|J27B.D1|FMC conn.|-|IO_L10N_T1_34|IO_L10N_T1_34|J27D.H26|FMC conn.||||-|IO_L10P_T1_34|IO_L10P_T1_34|J27D.H25|FMC conn.||||-|IO_L11N_T1_SRCC_34|IO_L11N_T1_SRCC_34|J27D.G3|FMC conn.||||-|IO_L11P_T1_SRCC_34|IO_L11P_T1_SRCC_34|J27D.G2|FMC conn.||||-|IO_L12N_T1_MRCC_34|IO_L12N_T1_MRCC_34|J27D.H5|FMC conn.||||-|IO_L12P_T1_MRCC_34|IO_L12P_T1_MRCC_34|J27D.H4|FMC conn.||||-|IO_L13N_T2_MRCC_34|'''IO_L13N_T1_MRCC_34'''|J27D.G7|FMC conn.||||-|IO_L13P_T2_MRCC_34|'''IO_L13P_T1_MRCC_34'''|J27D.G6|FMC conn.||||-|IO_L14N_T2_SRCC_34|IO_L14N_T2_SRCC_34|J27B.D9|FMC conn.||||-|IO_L14P_T2_SRCC_34|IO_L14P_T2_SRCC_34|J27B.D8|FMC conn.||||-|IO_L15N_T2_DQS_34|IO_L15N_T2_DQS_34|J27B.D21|FMC conn.||||-|IO_L15P_T2_DQS_34|IO_L15P_T2_DQS_34|J27B.D20|FMC conn.||||-|IO_L16N_T2_34|IO_L16N_T2_34|J27B.C23|FMC conn.||||-|IO_L16P_T2_34|IO_L16P_T2_34|J27B.C22|FMC conn.||||-|IO_L17N_T2_34|IO_L17N_T2_34|J27D.G22|FMC conn.||||-|IO_L17P_T2_34|IO_L17P_T2_34|J27D.G21|FMC conn.||||-|IO_L18N_T2_34|IO_L18N_T2_34|J27D.H20|FMC conn.||||-|IO_L18P_T2_34|IO_L18P_T2_34|J27D.H19|FMC conn.||||-| rowspan="2" |IO_L19N_T3_VREF_34| rowspan="2" |IO_L19N_T3_VREF_34|J27D.G19|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP21|TP SMD|-|IO_L19P_T3_34|n/a|n/a|At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.||||-|IO_L1N_T0_34|IO_L1N_T0_34|J27B.C19|FMC conn.||||-|IO_L1P_T0_34|IO_L1P_T0_34|J27B.C18|FMC conn.||||-|IO_L20N_T3_34|IO_L20N_T3_34|J27B.D18|FMC conn.||||-|IO_L20P_T3_34|IO_L20P_T3_34|J27B.D17|FMC conn.||||-|IO_L21N_T3_DQS_34|IO_L21N_T3_DQS_34|J27D.H17|FMC conn.||||-|IO_L21P_T3_DQS_34|IO_L21P_T3_DQS_34|J27D.H16|FMC conn.||||-|IO_L22N_T3_34|IO_L22N_T3_34|J27D.G16|FMC conn.||||-|IO_L22P_T3_34|IO_L22P_T3_34|J27D.G15|FMC conn.||||-|IO_L23N_T3_34|IO_L23N_T3_34|J27B.C11|FMC conn.||||-|IO_L23P_T3_34|IO_L23P_T3_34|J27B.C10|FMC conn.||||-|IO_L24N_T3_34|IO_L24N_T3_34|J27D.H23|FMC conn.||||-|IO_L24P_T3_34|IO_L24P_T3_34|J27D.H22|FMC conn.||||-|IO_L2N_T0_34|IO_L2N_T0_34|J27B.C15|FMC conn.||||-|IO_L2P_T0_34|IO_L2P_T0_34|J27B.C14|FMC conn.||||-|IO_L3N_T0_DQS_34|IO_L3N_T0_DQS_34|J27D.G13|FMC conn.||||-|IO_L3P_T0_DQS_PUDC_B_34(10K pull-up on SoM)|IO_L3P_T0_DQS_PUDC_B_34|J27D.G12|FMC conn.||||-|IO_L4N_T0_34|IO_L4N_T0_34|J27D.G10|FMC conn.||||-|IO_L4P_T0_34|IO_L4P_T0_34|J27D.G9|FMC conn.||||-|IO_L5N_T0_34|IO_L5N_T0_34|J27D.H11|FMC conn.||||-|IO_L5P_T0_34|IO_L5P_T0_34|J27D.H10|FMC conn.||||-| rowspan="2" |IO_L6N_T0_VREF_34| rowspan="2" |IO_L6N_T0_VREF_34|J27B.D15|FMC conn.||||-|TP22|TP SMD||||-|IO_L6P_T0_34|n/a|n/a|At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.||||-|IO_L7N_T1_34|IO_L7N_T1_34|J27D.H8|FMC conn.||||-|IO_L7P_T1_34|IO_L7P_T1_34|J27D.H7|FMC conn.||||-|IO_L8N_T1_34|IO_L8N_T1_34|J27D.H14|FMC conn.||||-|IO_L8P_T1_34|IO_L8P_T1_34|J27D.H13|FMC conn.||||-|IO_L9N_T1_DQS_34|IO_L9N_T1_DQS_34|J27B.D12|FMC conn.||||-|IO_L9P_T1_DQS_34|IO_L9P_T1_DQS_34|J27B.D11|FMC conn.||||-|||||||||-| rowspan="54" |35| rowspan="2" |IO_0_35| rowspan="2" |'''IO_0_VRN_35'''|J27C.F1|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.1|Header|-| rowspan="2" |IO_25_35| rowspan="2" |'''IO_25_VRP_35'''|J27E.K13|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|J31.3|Header|-|IO_L10N_T1_AD11N_35|IO_L10N_T1_AD11N_35|J27D.G34|FMC conn.|FPGA_BANK35_AD11N|JP32.3|Header|-|IO_L10P_T1_AD11P_35|IO_L10P_T1_AD11P_35|J27D.G33|FMC conn.|FPGA_BANK35_AD11P|JP32.1|Header|-|IO_L11N_T1_SRCC_35|IO_L11N_T1_SRCC_35|J27E.J3|FMC conn.||||-|IO_L11P_T1_SRCC_35|IO_L11P_T1_SRCC_35|J27E.J2|FMC conn.||||-|IO_L12N_T1_MRCC_35|IO_L12N_T1_MRCC_35|J27E.K5|FMC conn.||||-|IO_L12P_T1_MRCC_35|IO_L12P_T1_MRCC_35|J27E.K4|FMC conn.||||-|IO_L13N_T2_MRCC_35|IO_L13N_T2_MRCC_35|J27C.F5|FMC conn.||||-|IO_L13P_T2_MRCC_35|IO_L13P_T2_MRCC_35|J27C.F4|FMC conn.||||-|IO_L14N_T2_AD4N_SRCC_35|IO_L14N_T2_AD4N_SRCC_35|J27C.E3|FMC conn.|FPGA_BANK35_AD4N|JP30.16|Header|-|IO_L14P_T2_AD4P_SRCC_35|IO_L14P_T2_AD4P_SRCC_35|J27C.E2|FMC conn.|FPGA_BANK35_AD4P|JP30.14|Header|-|IO_L15N_T2_DQS_AD12N_35|IO_L15N_T2_DQS_AD12N_35|J27D.H38|FMC conn.|FPGA_BANK35_AD12N|JP32.8|Header|-|IO_L15P_T2_DQS_AD12P_35|IO_L15P_T2_DQS_AD12P_35|J27D.H37|FMC conn.|FPGA_BANK35_AD12P|JP32.6|Header|-|IO_L16N_T2_35|IO_L16N_T2_35|J27D.G37|FMC conn.||||-|IO_L16P_T2_35|IO_L16P_T2_35|J27D.G36|FMC conn.||||-|IO_L17N_T2_AD5N_35|IO_L17N_T2_AD5N_35|J27E.K8|FMC conn.|FPGA_BANK35_AD5N|JP31.1|Header|-|IO_L17P_T2_AD5P_35|IO_L17P_T2_AD5P_35|J27E.K7|FMC conn.|FPGA_BANK35_AD5P|JP30.15|Header|-|IO_L18N_T2_AD13N_35|IO_L18N_T2_AD13N_35|J27E.J7|FMC conn.|FPGA_BANK35_AD13N|JP32.9|Header|-|IO_L18P_T2_AD13P_35|IO_L18P_T2_AD13P_35|J27E.J6|FMC conn.|FPGA_BANK35_AD13P|JP32.7|Header|-| rowspan="2" |IO_L19N_T3_VREF_35| rowspan="2" |IO_L19N_T3_VREF_35|J27C.F8|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP24|TP SMD|-|IO_L19P_T3_35|IO_L19P_T3_35|J27C.F7|FMC conn.||||-|IO_L1N_T0_AD0N_35|IO_L1N_T0_AD0N_35|J27D.G25|FMC conn.|FPGA_BANK35_AD0P|JP30.4 |Header|-|IO_L1P_T0_AD0P_35|IO_L1P_T0_AD0P_35|PMOD_A5 J27D.G24|FMC conn.| FPGA_BANK35_AD0N|JP30.2|Header| -|IO_L20N_T3_AD6N_35|IO_L20N_T3_AD6N_35|J27C.E7|FMC conn.|FPGA_BANK35_AD6N|JP31.6|Header|-|IO_L20P_T3_AD6P_35|IO_L20P_T3_AD6P_35|J27C.E6|FMC conn.|FPGA_BANK35_AD6P|JP31.4|Header|-|IO_L21N_T3_DQS_AD14N_35|IO_L21N_T3_DQS_AD14N_35|J27E.K11|FMC conn.|FPGA_BANK35_AD14N|JP32.14|Header|-|IO_L21P_T3_DQS_AD14P_35|IO_L21P_T3_DQS_AD14P_35|J27E.K10|FMC conn.|FPGA_BANK35_AD14P|JP32.12|Header|-|IO_L22N_T3_AD7N_35|IO_L22N_T3_AD7N_35|J27E.J10|FMC conn.|FPGA_BANK35_AD7N|JP31.7|Header|-|IO_L22P_T3_AD7P_35|IO_L22P_T3_AD7P_35|J27E.J9|FMC conn.|FPGA_BANK35_AD7P|JP31.5|Header|-|IO_L23N_T3_35|IO_L23N_T3_35|J27C.F11|FMC conn.||||-|IO_L23P_T3_35|IO_L23P_T3_35|J27C.F10|FMC conn.||||-|IO_L24N_T3_AD15N_35|IO_L24N_T3_AD15N_35|J27C.E10|FMC conn.|FPGA_BANK35_AD15N|JP32.15|Header|-|IO_L24P_T3_AD15P_35|IO_L24P_T3_AD15P_35|J27C.E9|FMC conn.|FPGA_BANK35_AD15P|JP32.13|Header|-|IO_L2N_T0_AD8N_35|IO_L2N_T0_AD8N_35|J27B.D24|FMC conn.|FPGA_BANK35_AD8N|JP31.12|Header|-|IO_L2P_T0_AD8P_35|IO_L2P_T0_AD8P_35|J27B.D23|FMC conn.|FPGA_BANK35_AD8P|JP31.10|Header|-|IO_L3N_T0_DQS_AD1N_35|IO_L3N_T0_DQS_AD1N_35|J27D.H29|FMC conn.|FPGA_BANK35_AD1N|JP30.5|Header|-|IO_L3P_T0_DQS_AD1P_35|IO_L3P_T0_DQS_AD1P_35|J27D.H28|FMC conn.|FPGA_BANK35_AD1P|JP30.3|Header|-|IO_L4N_T0_35|IO_L4N_T0_35|J27D.G28|FMC conn.||||-|IO_L4P_T0_35|IO_L4P_T0_35|J27D.G27|FMC conn.||||-|IO_L5N_T0_AD9N_35|IO_L5N_T0_AD9N_35|J27B.D27|FMC conn.|FPGA_BANK35_AD9N|JP31.13|Header|-|IO_L5P_T0_AD9P_35|IO_L5P_T0_AD9P_35|J27B.D26|FMC conn.|FPGA_BANK35_AD9P|JP31.11|Header|-| rowspan="2" |IO_L6N_T0_VREF_35| rowspan="2" |IO_L6N_T0_VREF_35|J27B.C27|FMC conn.| rowspan="2" || rowspan="2" || rowspan="2" ||-|TP23|TP SMD|-|IO_L6P_T0_35|IO_L6P_T0_35|J27B.C26|FMC conn.||||-|IO_L7N_T1_AD2N_35|IO_L7N_T1_AD2N_35|J27D.H32|FMC conn.|FPGA_BANK35_AD2N|JP30.10|Header|-|IO_L7P_T1_AD2P_35|IO_L7P_T1_AD2P_35|J27D.H31|FMC conn.|FPGA_BANK35_AD2P|JP30.8|Header|-|IO_L8N_T1_AD10N_35|IO_L8N_T1_AD10N_35|J27D.G31|FMC conn.|FPGA_BANK35_AD10N|JP32.2|Header|-|IO_L8P_T1_AD10P_35|IO_L8P_T1_AD10P_35|J27D.G30|FMC conn.|FPGA_BANK35_AD10P|JP31.16|Header|-|IO_L9N_T1_DQS_AD3N_35|IO_L9N_T1_DQS_AD3N_35|J27D.H35|FMC conn.|FPGA_BANK35_AD3N|JP30.11|Header|-|IO_L9P_T1_DQS_AD3P_35|IO_L9P_T1_DQS_AD3P_35|J27D.H34|FMC conn.|FPGA_BANK35_AD3P|JP30.9|Header|-|||||||||-| rowspan="26" |13'''(not available on Zynq 7007S and 7010)'''|IO_L11P_T1_SRCC_13|'''IO_L23P_T3_13'''|JP17.3|PMOD [A]||||-|IO_L11N_T1_SRCC_13|'''IO_L23N_T3_13'''|JP17.4|PMOD [A]||||-|IO_L12P_T1_MRCC_13|'''IO_L9P_T1_DQS_13'''|JP17.2|PMOD [A]|IO_L9P_T1_DQS_13|J30.1|ONE PIECE|-|IO_L12N_T1_MRCC_13|'''IO_L9N_T1_DQS_13'''|JP17.1|PMOD [A]|IO_L9N_T1_DQS_13|J30.3|ONE PIECE|-|IO_L13P_T2_MRCC_13|'''IO_L7P_T1_13'''|JP17.7|PMOD [A]|IO_L7P_T1_13|J30.24|ONE PIECE|-|IO_L13N_T2_MRCC_13|'''IO_L7N_T1_13'''|JP17.8|PMOD [A]|IO_L7N_T1_13|J30.26|ONE PIECE|-|IO_L14P_T2_SRCC_13|'''IO_L15P_T2_DQS_13'''|n/a|ETH1_RXCK|IO_L15P_T2_DQS_13|J30.25|ONE PIECE|-|IO_L14N_T2_SRCC_13|'''IO_L15N_T2_DQS_13'''|n/a|ETH1_RXCTL|IO_L15N_T2_DQS_13|J30.27|ONE PIECE|-|IO_L15P_T2_DQS_13|'''IO_L5P_T0_13'''|JP17.6|PMOD [A]|IO_L5P_T0_13|J30.20|ONE PIECE|-|IO_L15N_T2_DQS_13|'''IO_L5N_T0_13'''|JP17.5 |PMOD [A]|IO_L5N_T0_13|J30.18|ONE PIECE|-|IO_L16N_T2_13|IO_L16N_T2_13|PMOD_A2 n/a|ETH1_TXCTL| IO_L16N_T2_13|J30.31|ONE PIECE| -|IO_L16P_T2_13|IO_L16P_T2_13|n/a|ETH1_TXCK|IO_L16P_T2_13|J30.29|ONE PIECE|-|IO_L17N_T2_13|IO_L17N_T2_13|n/a|ETH1_RXD1|IO_L17N_T2_13|J30.35|ONE PIECE|-|IO_L17P_T2_13|IO_L17P_T2_13|n/a|ETH1_RXD0|IO_L17P_T2_13|J30.33|ONE PIECE|-|IO_L18N_T2_13|IO_L18N_T2_13|n/a|ETH1_RXD3|IO_L18N_T2_13|J30.39|ONE PIECE|-|IO_L18P_T2_13|IO_L18P_T2_13|n/a|ETH1_RXD2|IO_L18P_T2_13|J30.37|ONE PIECE|-|IO_L19N_T3_VREF_13|IO_L19N_T3_VREF_13|n/a|ETH1_TXD1|IO_L19N_T3_VREF_13|J30.43|ONE PIECE|-|IO_L19P_T3_13|IO_L19P_T3_13|n/a|ETH1_TXD0|IO_L19P_T3_13|J30.41|ONE PIECE|-|IO_L20N_T3_13|IO_L20N_T3_13|n/a|ETH1_TXD3|IO_L20N_T3_13|J30.47|ONE PIECE|-|IO_L20P_T3_13|IO_L20P_T3_13|n/a|ETH1_TXD2|IO_L20P_T3_13|J30.45|ONE PIECE|-|IO_L21N_T3_DQS_13|IO_L21N_T3_DQS_13|n/a|ETH1_MDC|IO_L21N_T3_DQS_13|J30.51|ONE PIECE|-|IO_L21P_T3_DQS_13|IO_L21P_T3_DQS_13|n/a|ETH1_MDIO|IO_L21P_T3_DQS_13|J30.49|ONE PIECE|-|IO_L22N_T3_13|IO_L22N_T3_13|||IO_L22N_T3_13|J30.55|ONE PIECE|-|IO_L22P_T3_13|IO_L22P_T3_13|n/a|DWM_WIFI_IRQ|IO_L22P_T3_13|J30.53|ONE PIECE|-| rowspan="2" |IO_L6N_T0_VREF_13| rowspan="2" |IO_L6N_T0_VREF_13|JP23.3|PMOD [B]| rowspan="2" |IO_L6N_T0_VREF_13| rowspan="2" |J30.30| rowspan="2" |ONE PIECE|-|n/a|USB1_OC|} ==== BoraXEVB unavailable signals ====Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are '''not''' routed to the SoM due to the limited pin count of the SODIMM connector. {| class="wikitable"|+BoraXEVB's signal that are not available when mated with Bora Lite SoM!Bank!Carrier's signal
|-
|6 13||PMOD_A6 || || -IO_25_13
|-
|7 13||PMOD_A3 || || -IO_L1P_T0_13
|-
|8 13||PMOD_A7 || || -IO_L1N_T0_13
|-
|9, 10 13||DGND ||Ground || -IO_L2P_T0_13
|-
|11, 12 ||3.3V || || -|-|}==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:13{| class="wikitable" IO_L2N_T0_13