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__FORCETOC__<section begin="Body" />
== Reset scheme and voltage monitoring ==
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:Bora-reset-scheme-2.png | 900px]]
=== Reset signals ===
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
==== PS_MIO51_501 PS_MIO50_501 (USB PHY reset) ====By default, this signal is connected to the on-board ETH USB PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequence, even if FPGA is not programmedregardless of the PL status.
For example, this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> software routine generates an a hardware reset pulse. This initializes the component to its default register values and then it wil be correctly configured for properly working on BORA SOM.* Linux kernel will does not issue any further hardware reset the ethernet PHY issuing . If a software hardware reset via BCMR registeris required upon Linux boot up, the <code>phy-ulpi</code> kernel driver and/or the according device tree properties have to be modified for enabling this feature.
==== PS_MIO50_501 PS_MIO51_501 (Ethernet PHY reset) ====By default, this signal is connected to the on-board USB Ethernet PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequence, even if FPGA is not programmedregardless of the PL status.
For example, this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> software routine generates an a hardware reset pulse. This initializes the component to its default register values , which are partly determined by the PHY's strapping pins.* Upon boot up, the Linux kernel issues a software reset via the BCMR register. If a hardware reset is required instead, the <code>macb</code> kernel driver and then it wil /or the related device tree properties have to be correctly configured modified for properly working on BORA SOMenabling this feature.
=== Pins connection ===
* ethernet PHY (25 MHz)
* USB PHY (26 MHz)
Generally speaking, no clocks have to be provided by the carrier board.<section end="Body" />