Bureaucrats, dave_user, Administrators
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→SoC and SDRAM bank
|Frequency
[MHz]
|533(*)
|-
|Bus witdth
|2048
|}
(*) It is worth remembering that i.MX6DualLite/Solo could achieve better results in terms of memory bandwidth, even though their SDRAM bus frequency is lower (400 MHz). This is due to an errata of the ARM PL310 L2 cache controller. This bug is not present in the i.MX6DualLite/Solo SoC's, which integrate a newer version of the controller.
===Software configuration===
