Bureaucrats, dave_user, Administrators
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→pmbw
*http://mirror.dave.eu/axel/SBCX-TN-006/pmbw-stats-AxelLite-i.MX6Q-996MHz.txt
*http://mirror.dave.eu/axel/SBCX-TN-006/pmbw-plots-AxelLite-i.MX6Q-996MHz.pdf
Generally speaking, all the charts confirms a vertical drop of the performances when the array size is greater than the L2 cache.
For more details about <code>pmbw</code>, please refer to [https://panthema.net/2013/pmbw/ this page].
