Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→Testbed general configuration
==Testbed general configuration==
This section illustrates the configuration settings common to all the tests that were performed. Basically, the testbed that was used is the same described in [[MISCSBCX-TN-008004:_Running_Debian_Buster__Running_Armbian_Buster_(armbianDebian_10)_on_Mito8M|this TN]].
===SoC and SDRAM bank===
The SoC model is i.MX8M Quad:
<pre class="board-terminal">
armbian@Mito8Msbcx:~/devel/stream/lmbench/tmp$ lscpuArchitecture: aarch64armv7l
Byte Order: Little Endian
CPU(s): 4
Core(s) per socket: 4
Socket(s): 1
Vendor ID: ARM
Model: 410Model name: Cortex-A53A9Stepping: r0p4r2p10CPU max MHz: 1300996.0000CPU min MHz: 800396.0000BogoMIPS: 167.66L1d cache: unknown sizeL1i cache: unknown sizeL2 cache: unknown sizeNUMA node0 CPU(s): 0-354Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuidhalf thumb fastmult vfp edsp neon vfpv3 tls vfpd32
</pre>
This processor is capable of running either at 800 MHz or 1.3 GHzdifferent speeds. All the tests were conducted at 800 996 MHz.
The following table details the characteristics of the SDRAM bank connected to the SoC.
