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{{AppliesToAxel}}
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{{WarningMessage|text=This technical note was validated against specific versions of hardware and software. What is described here may not work with other versions.}}
|Frequency
[MHz]
|533(*)
|-
|Bus witdth
|2048
|}
(*) It is worth remembering that i.MX6DualLite/Solo could achieve better results in terms of memory bandwidth, even though their SDRAM bus frequency is lower (400 MHz). This is due to an errata of the ARM PL310 L2 cache controller. This bug is not present in the i.MX6DualLite/Solo SoC's, which integrate a newer version of the controller.
===Software configuration===
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The most interesting results to consider are those that refer to a buffer sizes exceeding 1MB, which is the size of the L2 cache. Approximately, read bandwidth is 630MB/s (7.8% efficiency), while write bandwidth is 2080 MB/s (25.7% efficiency). These numbers are significantly different that the ones provided by STREAM. This confirms once again that such results are strongly dependent on the implementation of the test used to determine the bandwidth.
For more information regarding LMbench, please see [http://lmbench.sourceforge.net/ this page].
*http://mirror.dave.eu/axel/SBCX-TN-006/pmbw-plots-AxelLite-i.MX6Q-996MHz.pdf
Generally speaking, all the charts confirms a vertical drop of exhibit significant declines in the performances when the array size is greater than around the L1 and the L2 cachesize.
For more details about <code>pmbw</code>, please refer to [https://panthema.net/2013/pmbw/ this page].
====Building====
To build STREAM:
* clone its git repository
*modify the <code>Makefile</code> as shown below
*issue the <code>make</code> command.
<pre class="board-terminal">
git clone https://github.com/jeffhammond/STREAM.git
===pmbw===
====Building====
Building pmbw is straightforward. Please click on ''Expand'' to show the box that illustrates the procedure.
<pre class="board-terminal mw-collapsible mw-collapsed">
armbian@sbcx:~/devel/pmbw$ git clone https://github.com/bingmann/pmbw.git
