Difference between revisions of "Reset scheme (Bora/BoraLite)"
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== Reset scheme and voltage monitoring == | == Reset scheme and voltage monitoring == | ||
The following picture shows the simplified block diagram of reset scheme and voltage monitoring. | The following picture shows the simplified block diagram of reset scheme and voltage monitoring. | ||
Revision as of 15:32, 24 March 2014
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Reset scheme and voltage monitoring[edit | edit source]
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
Two reset signals are available. They are described in detail in the following sections.
PORSTn[edit | edit source]
This is a bidirectonal open-drain signal that is connected to Zynq's PS_SRST_B and can be asserted by the following devices:
- a multi-rail voltage monitor that monitors 3.3VIN power rails and all of the rails generated by Bora's PSU. This monitor
- in case of a power glitch, asserts MEM_WPn signal in order to prevent any spurious write operation on flash memories too. MEM_WPn is 3.3V, push-pull, active low.
- has a timeout of about 1ms.
- provides MRSTn debounced input for manual reset (for example to connect a push-button). This signal is pulled-up to 3.3VIN through a 2.2kOhm resistor.
- a watchdog timer (Maxim MAX6373). For more details please refer to Watchdog section.
PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.
SYS_RSTn[edit | edit source]
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
