Difference between revisions of "Reset scheme (Bora/BoraLite)"
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By default, this signal is connected to on-board ETH PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. | By default, this signal is connected to on-board ETH PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. | ||
| − | U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it | + | U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it will be correctly configured for properly working on BORA SOM. |
| − | Linux kernel will reset the ethernet PHY issuing a software reset via BCMR register. | + | Linux kernel will reset the ethernet PHY issuing a software reset via BCMR register. If a hardware reset is required, the <code>macb</code> kernel driver and/or the device tree properties have to be modified for including this functionality. |
==== PS_MIO50_501 ==== | ==== PS_MIO50_501 ==== | ||
By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. | By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. | ||
| − | U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it | + | U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it will be correctly configured for properly working on BORA SOM. |
| + | |||
| + | If a hardware reset is required, the <code>phy-ulpi</code> kernel driver and/or the device tree properties have to be modified for including this functionality. | ||
=== Pins connection === | === Pins connection === | ||
Revision as of 13:37, 14 April 2022
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Contents
Reset scheme and voltage monitoring[edit | edit source]
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
Reset signals[edit | edit source]
The available reset signals are described in detail in the following sections.
MRST[edit | edit source]
MRSTn is a de-bounced input for manual reset (for example to connect a push-button). This signal connected to the voltage monitor and is pulled-up to 3.3VIN through a 2.2kOhm resistor.
PORSTn[edit | edit source]
This is a bidirectonal open-drain signal that is connected to Zynq's PS_POR_B and can be asserted by the following devices:
- a multi-rail voltage monitor that monitors 3.3VIN power rails and all of the rails generated by Bora's PSU. This monitor
- in case of a power glitch, asserts MEM_WPn signal in order to prevent any spurious write operation on flash memories too. MEM_WPn is 3.3V, push-pull, active low.
- has a timeout (set through an on-board capacitor) of about 200 ms.
- provides MRSTn debounced input for manual reset (for example to connect a push-button). This signal is pulled-up to 3.3VIN through a 2.2kOhm resistor.
- a watchdog timer (Maxim MAX6373). For more details please refer to Watchdog section.
PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.
SYS_RSTn[edit | edit source]
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
PS_MIO51_501[edit | edit source]
By default, this signal is connected to on-board ETH PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed.
U-Boot board_init software routine generates an hardware reset pulse. This initializes the component to its default register values and then it will be correctly configured for properly working on BORA SOM.
Linux kernel will reset the ethernet PHY issuing a software reset via BCMR register. If a hardware reset is required, the macb kernel driver and/or the device tree properties have to be modified for including this functionality.
PS_MIO50_501[edit | edit source]
By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed.
U-Boot board_init software routine generates an hardware reset pulse. This initializes the component to its default register values and then it will be correctly configured for properly working on BORA SOM.
If a hardware reset is required, the phy-ulpi kernel driver and/or the device tree properties have to be modified for including this functionality.
Pins connection[edit | edit source]
| Pin Name | Bora Pin | Bora Lite Pin |
| MRST | J2.116 | J1.20 |
| PORSTn | J2.114 | J1.20 (alternate mount option) |
| SYS_RSTn | J2.112 | J1.18 |
| PS_MIO51_501 | J2.106 | J1.75 |
| PS_MIO50_501 | J2.106 | - |
Clock scheme[edit | edit source]
Bora is equipped with three independent active oscillators:
- processor (33.3 MHz)
- ethernet PHY (25 MHz)
- USB PHY (26 MHz)
Generally speaking, no clocks have to be provided by carrier board.
