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Two The available reset signals are available. They are described in detail in the following sections.
→Reset scheme and voltage monitoring
[[File:Bora-reset-scheme.png | 700px]]
=== MRST (J2.116) ===MRSTn is a de-bounced input for manual reset (for example to connect a push-button). This signal connected to the voltage monitor and is pulled-up to 3.3VIN through a 2.2kOhm resistor. === PORSTn (J2.114) ===
This is a bidirectonal open-drain signal that is connected to Zynq's PS_SRST_B and can be asserted by the following devices:
* a multi-rail voltage monitor that monitors 3.3VIN power rails and all of the rails generated by Bora's PSU. This monitor
PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.
=== SYS_RSTn (J2.112) ===
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
=== PS_MIO51_501 (J2.106) ===
By default, this signal is connected to on-board ETH PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department sales.
=== PS_MIO50_501 (J2.104) ===
By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department sales.
