Bureaucrats, dave_user, Administrators
8,150
edits
Changes
no edit summary
{{Applies To BoraLite}}
{{InfoBoxBottom}}
__FORCETOC__
<section begin="Body" />
== Reset scheme and voltage monitoring ==
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:Bora-reset-scheme-2.png | 900px]]
=== Reset signals ===
The available reset signals are described in detail in the following sections.
==== MRST ====
MRSTn is a de-bounced input for manual reset (for example to connect a push-button). This signal connected to the voltage monitor and is pulled-up to 3.3VIN through a 2.2kOhm resistor.
==== PORSTn ====
This is a bidirectonal open-drain signal that is connected to Zynq's PS_POR_B and can be asserted by the following devices:
* a multi-rail voltage monitor that monitors 3.3VIN power rails and all of the rails generated by Bora's PSU. This monitor
PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.
==== SYS_RSTn ====
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
=== PS_MIO51_501 = PS_MIO50_501 (USB PHY reset) ====By default, this signal is connected to the on-board ETH USB PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department salesregardless of the PL status.
==== PS_MIO51_501 (Ethernet PHY reset) ====By default, this signal is connected to the on-board Ethernet PHY reset input as depicted in the above figure. This scheme allows complete software control of the PHY hardware reset regardless of the PL status. For example, this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> routine generates a hardware reset pulse. This initializes the component to its default register values, which are partly determined by the PHY's strapping pins.* Upon boot up, the Linux kernel issues a software reset via the BCMR register. If a hardware reset is required instead, the <code>macb</code> kernel driver and/or the related device tree properties have to be modified for enabling this feature. === Pins connection ===
{| class="wikitable" {| {{table}}
|-
|}
=== Clock scheme ===
Bora is equipped with three independent active oscillators:
* processor (33.3 MHz)
* ethernet PHY (25 MHz)
* USB PHY (26 MHz)
Generally speaking, no clocks have to be provided by the carrier board.
<section end="Body" />
