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{{Applies To Bora}}
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== Reset scheme and voltage monitoring ==
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:Bora-reset-scheme-2.png | 700px900px]]
=== Reset signals ===
The available reset signals are described in detail in the following sections.
==== MRST (J2.116) ====
MRSTn is a de-bounced input for manual reset (for example to connect a push-button). This signal connected to the voltage monitor and is pulled-up to 3.3VIN through a 2.2kOhm resistor.
==== PORSTn (J2.114) ====This is a bidirectonal open-drain signal that is connected to Zynq's PS_SRST_B PS_POR_B and can be asserted by the following devices:
* a multi-rail voltage monitor that monitors 3.3VIN power rails and all of the rails generated by Bora's PSU. This monitor
** in case of a power glitch, asserts MEM_WPn signal in order to prevent any spurious write operation on flash memories too. MEM_WPn is 3.3V, push-pull, active low.
** has a timeout (set through an on-board capacitor) of about 1ms200 ms.
** provides MRSTn debounced input for manual reset (for example to connect a push-button). This signal is pulled-up to 3.3VIN through a 2.2kOhm resistor.
* a watchdog timer (Maxim MAX6373). For more details please refer to [[Watchdog_(Bora)|Watchdog]] section.
PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.
==== SYS_RSTn (J2.112) ====
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
=== PS_MIO51_501 = PS_MIO50_501 (J2.106USB PHY reset) ====By default, this signal is connected to the on-board ETH USB PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department salesregardless of the PL status.
For example, this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> routine generates a hardware reset pulse. This initializes the component to its default register values. * Linux kernel does not issue any further hardware reset. If a hardware reset is required upon Linux boot up, the <code>phy-ulpi</code> kernel driver and/or the according device tree properties have to be modified for enabling this feature. === PS_MIO50_501 = PS_MIO51_501 (J2.104Ethernet PHY reset) ====By default, this signal is connected to the on-board USB Ethernet PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequenceregardless of the PL status. For example, even if FPGA this is how the reset signal is not programmedhandled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> routine generates a hardware reset pulse. In case this signals must be used This initializes the component to implement different functions on carrier boardits default register values, alternative routing schemes which are available on request in order partly determined by the PHY's strapping pins.* Upon boot up, the Linux kernel issues a software reset via the BCMR register. If a hardware reset is required instead, the <code>macb</code> kernel driver and/or the related device tree properties have to free be modified for enabling this signalfeature. === Pins connection === {| class="wikitable" {| {{table}}| style="background:#f0f0f0;" align="center" |'''Pin Name'''| style="background:#f0f0f0;" align="center" |'''Bora Pin'''| style="background:#f0f0f0;" align="center" |'''Bora Lite Pin'''|-|MRST || J2.116 || J1.20|-|PORSTn || J2.114 || J1.20 (alternate mount option)|-|SYS_RSTn || J2.112 || J1.18|-|PS_MIO51_501 || J2.106 || J1.75|-|PS_MIO50_501 || J2.106 || -|-|} === Clock scheme ===Bora is equipped with three independent active oscillators:* processor (33. For more details please refer 3 MHz)* ethernet PHY (25 MHz)* USB PHY (26 MHz)Generally speaking, no clocks have to department salesbe provided by the carrier board.<section end="Body" />
