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__FORCETOC__<section begin="Body" />
== Reset scheme and voltage monitoring ==
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:Bora-reset-scheme-2.png | 900px]]
=== Reset signals ===
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
==== PS_MIO51_501 PS_MIO50_501 (USB PHY reset) ====By default, this signal is connected to the on-board ETH USB PHY reset inputas depicted in the above figure. This scheme allows complete software control of PHY reset sequence, even if FPGA is not programmed. U-Boot <code>board_init</code> software routine generates an hardware reset pulse. This initializes the component to its default register values and then it will be correctly configured for properly working on BORA SOM.Linux kernel will reset the ethernet PHY issuing a software reset via BCMR register. If a hardware reset is required, the <code>macb</code> kernel driver and/or regardless of the device tree properties have to be modified for including this functionalityPL status.
For example, this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> routine generates a hardware reset pulse. This initializes the component to its default register values, which are partly determined by the PHY's strapping pins.* Upon boot up, the Linux kernel issues a software reset via the BCMR register. If a hardware reset is requiredinstead, the <code>phy-ulpimacb</code> kernel driver and/or the related device tree properties have to be modified for including enabling this functionalityfeature.
=== Pins connection ===
* ethernet PHY (25 MHz)
* USB PHY (26 MHz)
Generally speaking, no clocks have to be provided by the carrier board.<section end="Body" />
