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__FORCETOC__<section begin="Body" />
== Reset scheme and voltage monitoring ==
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:Bora-reset-scheme-2.png | 900px]]
=== Reset signals ===
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
==== PS_MIO51_501 PS_MIO50_501 (USB PHY reset) ====By default, this signal is connected to the on-board ETH USB PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequenceregardless of the PL status. For example, even if FPGA this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> routine generates a hardware reset pulse. This initializes the component to its default register values. * Linux kernel does not programmedissue any further hardware reset. In case If a hardware reset is required upon Linux boot up, the <code>phy-ulpi</code> kernel driver and/or the according device tree properties have to be modified for enabling this signals must be used feature. ==== PS_MIO51_501 (Ethernet PHY reset) ====By default, this signal is connected to implement different functions the on carrier -board, alternative routing schemes are available on request Ethernet PHY reset input as depicted in order to free this signalthe above figure. For more details please refer to department salesThis scheme allows complete software control of the PHY hardware reset regardless of the PL status.
=== Pins connection ===
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=== Clock scheme ===Bora is equipped with three independent active oscillators:* processor (33.3 MHz)* ethernet PHY (25 MHz)* USB PHY (26 MHz)Generally speaking, no clocks have to be provided by the carrier board.<section end="Body" />
