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→PS_MIO50_501 (USB PHY reset)
By default, this signal is connected to the on-board USB PHY reset input as depicted in the above figure. This scheme allows complete software control of the PHY hardware reset regardless of the PL status.
For example, this is how the reset signal is handled in the TBD (inserire riferimento al preciso BSP analizzatoe link ai sorgenti):
* U-Boot <code>board_init</code> routine generates a hardware reset pulse. This initializes the component to its default register values.
* Linux kernel does not issue any further hardware reset. If a hardware reset is required upon Linux boot up, the <code>phy-ulpi</code> kernel driver and/or the according device tree properties have to be modified for enabling this feature.
By default, this signal is connected to the on-board Ethernet PHY reset input as depicted in the above figure. This scheme allows complete software control of the PHY hardware reset regardless of the PL status.
For example, this is how the reset signal is handled in the TBD (inserire riferimento al preciso BSP analizzatoe link ai sorgenti):
* U-Boot <code>board_init</code> routine generates a hardware reset pulse. This initializes the component to its default register values, which are partly determined by the PHY's strapping pins.
* Upon boot up, the Linux kernel issues a software reset via the BCMR register. If a hardware reset is required instead, the <code>macb</code> kernel driver and/or the related device tree properties have to be modified for enabling this feature.
* ethernet PHY (25 MHz)
* USB PHY (26 MHz)
Generally speaking, no clocks have to be provided by the carrier board.
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