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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.1
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Apr 2022
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Updated USB and ETH PHY reset information
|}
<section end="History" />
<section begin=Reset/>
== Reset scheme and voltage monitoring ==
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:Borax-reset-scheme-2.png|thumb|center|600px]] === Reset signals ===
The available reset signals are described in detail in the following sections.
==== MRSTn (J2.116) ====
MRSTn is a de-bounced input for manual reset (for example to connect a push-button). This signal connected to the voltage monitor and is pulled-up to 3.3VIN through a 2.2kOhm resistor.
==== PORSTn (J2.114) ====
This is a bidirectonal open-drain signal that is connected to Zynq's PS_SRST_B and can be asserted by the following devices:
* a multi-rail voltage monitor that monitors 3.3VIN power rails and all of the rails generated by Bora Xpress's PSU. This monitor
** has a timeout (set through an on-board capacitor) of about 200 ms.
** provides MRSTn debounced input for manual reset (for example to connect a push-button). This signal is pulled-up to 3.3VIN through a 2.2kOhm resistor.
* a watchdog timer (Maxim MAX6373). For more details please refer to [[Watchdog_(BoraXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Watchdog|Watchdog]] section.
PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.
==== SYS_RSTn (J2.112) ====
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
==== PS_MIO51_501 (Ethernet PHY reset) ====
By default, this signal is connected to the on-board Ethernet PHY reset input as depicted in the above figure. This scheme allows complete software control of the PHY hardware reset regardless of the PL status.
=== SYS_RSTn = PS_MIO50_501 (J2.112USB PHY reset) ====This By default, this signal is connected to Zynq's PS_SRST_B and is pulledthe on-up to 1board USB PHY reset input as depicted in the above figure.8V through a 20kOhm resistorThis scheme allows complete software control of the PHY hardware reset regardless of the PL status.
For example, this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid== PS_MIO51_501 (J214810 BELK 4.1.106) ===5]: By default, this signal is connected to on* U-board ETH PHY Boot <code>board_init</code> routine generates a hardware reset inputpulse. This allows complete software control of PHY initializes the component to its default register values. * Linux kernel does not issue any further hardware reset. If a hardware reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier boardrequired upon Linux boot up, alternative routing schemes are available on request in order the <code>phy-ulpi</code> kernel driver and/or the according device tree properties have to free be modified for enabling this signal. For more details please refer to department salesfeature.
==Clock scheme = PS_MIO50_501 =Bora is equipped with three independent active oscillators:* processor (J233.1043 MHz)* ethernet PHY (25 MHz) ===By default, this signal is connected to on-board * USB PHY reset input. This allows complete software control of PHY reset sequence(26 MHz)Generally speaking, even if FPGA is not programmed. In case this signals must no clocks have to be used to implement different functions on provided by the carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department sales.<section end=Reset/>