Changes

<section begin=Body"History" />{| style="border-collapse:collapse; "! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History|- ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes|-| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.1| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Apr 2022| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Updated USB and ETH PHY reset information|}<section end="History" /> <section begin=Reset/>

[[File:Borax-reset-scheme-2.png|thumb|center|600px]]

==== PS_MIO51_501 (J2.106Ethernet PHY reset) ====By default, this signal is connected to the on-board ETH Ethernet PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequenceregardless of the PL status.  For example, even if FPGA this is not programmedhow the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> routine generates a hardware reset pulse. In case this signals must be used This initializes the component to implement different functions on carrier boardits default register values, alternative routing schemes which are available on request in order partly determined by the PHY's strapping pins.* Upon boot up, the Linux kernel issues a software reset via the BCMR register. If a hardware reset is required instead, the <code>macb</code> kernel driver and/or the related device tree properties have to free be modified for enabling this feature. ==== PS_MIO50_501 (USB PHY reset) ====By default, this signalis connected to the on-board USB PHY reset input as depicted in the above figure. For more details please refer to department salesThis scheme allows complete software control of the PHY hardware reset regardless of the PL status.

For example, this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=== PS_MIO50_501 (J214810 BELK 4.1.104) ====5]: By default, this signal is connected to on* U-board USB PHY Boot <code>board_init</code> routine generates a hardware reset inputpulse. This allows complete software control of PHY initializes the component to its default register values. * Linux kernel does not issue any further hardware reset. If a hardware reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier boardrequired upon Linux boot up, alternative routing schemes are available on request in order the <code>phy-ulpi</code> kernel driver and/or the according device tree properties have to free be modified for enabling this signal. For more details please refer to department salesfeature.

== Clock scheme ==

<section end=BodyReset/>