Changes

Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.

=== Handling CPU -initiated software reset ==='''By default, MX6 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''. This behaviour can be changed by acting on WDOG_RESET_B_DEB signal configuration. This signal For these reasons, it is driven by MX6strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

The two typical scenarios are:# WDOG_RESET_B_DEB This technique is not used implemented in [[Axel_Embedded_Linux_Kit_(defaultXELK): in this case a CPU initiated reset sequence does not reset external devices such as SPI NOR flash memory|XELK]]. '''This may be critical'''. For example if boot memory is not At software level, U-Boot and Linux kernel software reset properly, routines make use of processor might be unable 's WDT #2 to boot correctlyassert the WDOG2_B reset signal.# WDOG_RESET_B_DEB is used: in this case a CPU initiated reset asserts WDOG_RESET_B_DEB This signal that, in turn, can be used is routed to reset external devicesGPIO_1 pad (MUX mode = 1). To implement this solution:#* software reset routines must configure WDT in order to assert WDOG_RESET_B_DEB signal#* WDOG_RESET_B_DEB must be configured properly at IOMUX controller At hardware level#* when asserted, WDOG_RESET_B_DEB must assert in turn either AxelLite's PMIC_PWRON or AxelLite's CPU_PORn this signal at carrier board level is AC-coupled to a 3-state output buffer (see please refer to U22 chip of [[AxelEVB-Lite]] schematics as an examplecarrier board). In case , driving PMIC_PWRON is asserted, a complete power on cycle is perfomed and PMIC is reset too. In case CPU_PORn is asserted instead, PMIC is not reset because its RESETBMCU pad is output only. WDOG_RESET_B_DEB can be routed to SD1_DATA2 or SD1_DATA3 pads. For more details please see descriptions ofIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 and IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 registers in chapter ''IOMUX controller'' of processor Reference Manual. About WDT, please refer to ''Watchdog Timer'' chapter instead.